Well, it has been a little bit disappointing, because though there were near 100 works, only four of them were on compact modeling. However, the rest of all has been very interesting, and I've learn more than I ever wanted to know about fabrication processes...
Once everything is added up, I'd like to point out some papers: one of Plastic Logic, Ltd where they were presenting statistics about defects in their fabricated circuits (panels), and another from Canon and the Tokyo Institute of Technology.
The latter was about parameter dispersion on TFT, one thing I believe to be quite forgotten about in compact modeling and very (VERY) important for design. The paper is good, but it lets out many things (effects of separation, orientation, mismatch in size, correlations among variations, etc...) However, it is a good start.
Jan 29, 2007
Jan 23, 2007
The European Network of Excellence "SINANO" addressed Compact Modelling of Multiple-Gate MOSFETs
From January 2004 to December 2006, a number of European teams have been working together in a Network of Excellence called SINANO, devoted to the study of novel structures of Silicon nanodevices.
The work has included technology, characterization, advanced simulation and compact modeling of novel structures of nanoscale MOSFETs.
The compact modeling work has especially addressed Multuple-Gate MOSFETs, in particular Double-Gate (DG) and Gate All Around (GAA) MOSFETs. The joint effort on compact modeling has led to several publications in international journals and conference proceedings.
Among the compact modeling publications carried out under the umbrella of the SINANO Network of Excellence, I want to mention the following paper, which was invited to the Special Issue on Advanced Compact Models and 45-nm Modeling Challenges, of IEEE Transactions on Electron Devices:
B. Iñiguez, T. A., Fjeldly, A. Lazaro, F. Danneville and M. J. Deen, “Compact-modeling solutions for nanoscale double-gate and gate-all-around MOSFETs,” IEEE Trans. on Electron Devices, vol 53, no. 9, pp. 2128-2142 September 2006
The work has included technology, characterization, advanced simulation and compact modeling of novel structures of nanoscale MOSFETs.
The compact modeling work has especially addressed Multuple-Gate MOSFETs, in particular Double-Gate (DG) and Gate All Around (GAA) MOSFETs. The joint effort on compact modeling has led to several publications in international journals and conference proceedings.
Among the compact modeling publications carried out under the umbrella of the SINANO Network of Excellence, I want to mention the following paper, which was invited to the Special Issue on Advanced Compact Models and 45-nm Modeling Challenges, of IEEE Transactions on Electron Devices:
B. Iñiguez, T. A., Fjeldly, A. Lazaro, F. Danneville and M. J. Deen, “Compact-modeling solutions for nanoscale double-gate and gate-all-around MOSFETs,” IEEE Trans. on Electron Devices, vol 53, no. 9, pp. 2128-2142 September 2006
(This is an excellent review of the compact modeling work carried so far in Multiple-Gate devices and provides very interesting solutions for a 2-D or 3-D analytical model)
ITC in Rome
Well, today I'm leaving for the International Thin-Film Transistor in Rome, so the blog is going to be un-updated until I come back. However, I promise a (quite) full report when I return.
Jan 22, 2007
A historical note
This post is a historical hint. This weekend I've been surfing the internet, and I've been looking for some pages on Spice history. Why Spice? Well, all of you know that if spice (or similar) didn't exist, then probably the semiconductor revolution wouldn't have taken place. The first link is to the wikipedia, where they put a quite extensive article about it, including even a list of commercial and free simulators. Only a little comment: In the list they include Eldo, and I think that I should note that, while Eldo is in fact a simulator, it is one of the few that is not Spice-based. Another link is to the page of ecircuitcenter, where they put quite the same information, but in the format of list, which is maybe clearer.
The basic facts about the name "Spice" are few: created as a class project by Larry Nagel (under supervision of Ron Rohrer) it was first called CANCER (Computer Analysis of Non-Linear Circuits Excluding Radiation), because of the time it was created. In 1972 (yes, that's before I was born...), the final name SPICE (Simulation Program with IC Emphasis) was introduced. And that's all about the name. Another day, I'll talk about other features of this simulator.
The basic facts about the name "Spice" are few: created as a class project by Larry Nagel (under supervision of Ron Rohrer) it was first called CANCER (Computer Analysis of Non-Linear Circuits Excluding Radiation), because of the time it was created. In 1972 (yes, that's before I was born...), the final name SPICE (Simulation Program with IC Emphasis) was introduced. And that's all about the name. Another day, I'll talk about other features of this simulator.
Jan 18, 2007
Language of choice
I agree with the post from Marek Mierzwinski (below) from Tiburon Design Automation. Moreover, we people working on compact modelling should agree to use all the same language of choice. However, the nice thing about standards is having so many to choose from...
Anyway, there is a question I would like to point out: model development should be done in a language that allows easy integration with commercial simulators. Up to here, both Verilog and HDLs meet the requirements. However, the last step for a model (when it comes of age or it has been accepted by the community as the ideal model for a given device), must be to be implemented in a (many) simulator as a built-in option. In this case, obviously, implementation must be done in some lower-level language like C/C++/Fortran/etc... Otherwise, the simulator will be too sloooooowwwww to simulate large circuits.
Anyway, there is a question I would like to point out: model development should be done in a language that allows easy integration with commercial simulators. Up to here, both Verilog and HDLs meet the requirements. However, the last step for a model (when it comes of age or it has been accepted by the community as the ideal model for a given device), must be to be implemented in a (many) simulator as a built-in option. In this case, obviously, implementation must be done in some lower-level language like C/C++/Fortran/etc... Otherwise, the simulator will be too sloooooowwwww to simulate large circuits.
Jan 15, 2007
More DG
I've been looking at a not very known journal: the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, from Wiley. I've found an useful paper from the EKV people: "Explicit modelling of the double-gate MOSFET with VHDL-AMS". It is in the vol 19, issue 3 (may/june 2006). It seems that going VHDL is the future for all those implementing models, at least in the first stages. I agree with this trend, because it is much easier to use than trying to tie your C-code inside programs like HSPICE or Intusoft's simulator IsSpice. Moreover, it is also easier to depure and also it is easier to test the models. In some days, I should post something about model testing...
In the same issue, there is also another interesting paper about accurate substrate modelling for RF applications.
In the same issue, there is also another interesting paper about accurate substrate modelling for RF applications.
Jan 11, 2007
Undoped Double-Gate MOSFETs
It seems that this is the star subject in compact modelling in both Solid-State Electronics from Elsevier and the IEEE Transactions on Electron Devices. I have seen at least four different papers on the subject.
I think that the more interesting one among them is "A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs", from Adelmo Ortiz-Conde et al. I believe this for two reasons: the first one is that it is very convenient having a review of the state-of-the-art from time to time, and the second reason is that they are, probably, one of the best people to do this review, because they were one of the first research groups to work on this subject.
I think that the more interesting one among them is "A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs", from Adelmo Ortiz-Conde et al. I believe this for two reasons: the first one is that it is very convenient having a review of the state-of-the-art from time to time, and the second reason is that they are, probably, one of the best people to do this review, because they were one of the first research groups to work on this subject.
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