Parasitic Capacitance Analytical #Modeling for Sub-7-nm Multigate Devices https://t.co/z8Q8IcuINM

Parasitic Capacitance Analytical #Modeling for Sub-7-nm Multigate Devices https://t.co/z8Q8IcuINM

— Wladek Grabinski (@wladek60) January 22, 2016

from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:47PM
via IFTTT

Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices #modeling https://t.co/9Q50HGFkni

Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices #modeling https://t.co/9Q50HGFkni

— Wladek Grabinski (@wladek60) January 22, 2016

from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:44PM
via IFTTT

FOSDEM 2016 EDA Devroom

FOSDEM 2016: EDA Devroom

Room: AW1.121 

Saturday, 30 January 2016

Software developers have a much easier time sharing their developments than hardware designers. When you put a piece of code on the Web, you don't ask yourself if others will have the freedom and resources to access a text editor to look at it and modify it, or a compiler or interpreter to have the code do something useful. The landscape for hardware designs is more complicated. The dominant design and simulation tools are proprietary, and there is not even a de-facto proprietary standard format to share designs. The Electronic Design Automation (EDA) Devroom looks at recent progress in Free CAD/EDA Tools for hardware design and simulation, and serves as a meeting place for discussion about future collaborations and FOSS developments. Come and see how some of these tools are actually catching up, and sometimes even more, in terms of features and quality.

[EDA Devroom Detailed Agenda]

NEEDS Berkeley Workshop 2016

Modelling using Verilog-A in MAPP: A Hands-On Workshop

8 AM - 6 PM

Thursday, Feb 4, 2016

University of California, Berkeley

Hughes Room, 400 Cory Hall

Berkeley, CA 94720

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Berkeley's Model and Algorithm Prototyping Platform (MAPP) is a MATLAB-based platform that provides a complete environment for developing, testing, experimentally validating, and inserting compact models in open source simulation platforms. It is also useful for prototyping new simulation algorithms.

This hands-on workshop will focus on the newly developed Verilog-A to ModSpec device model translator for MAPP, dubbed VAPP (Verilog-A Parser and Processor). The goal of the workshop is to illustrate how VAPP/MAPP facilitates the development of simulation ready compact models. An overview of MAPP's multi-physics modelling and simulation capabilities will also be provided. A hands-on refresher on MAPP will be provided for those who have no prior experience with it.

Please bring your laptop (running linux, OSX or Windows). It would be very helpful if you already have MATLAB installed and running on your laptop; otherwise you may need to access the hands-on components through the web.

For more information about MAPP, see: https://nanohub.org/groups/needs/mapp

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Travel support will be available for NEEDS students. Please try to share a room, and ask your advisor to e-mail Mark Lundstrom at lundstro@purdue.edu for travel support.

For other questions, please contact Vicki Johnson at vicki@purdue.edu

[video] How to Model RF Passive Components: Capacitors and Resistors

This video explains and demonstrates a method to develop accurate SPICE models from verified S-parameter measurements. By using an easy to follow, step by step procedure, this video walks you through the entire modeling flow for an on-wafer capacitor, using the Keysight Measurement and Modeling Software IC-CAP.

The IC-CAP project can be downloaded, together with a detailed How-to-Use description, and an in-depth tutorial about passive components modeling, applying the demonstrated method.

[VIDEO]

[mos-ak] [Final Program] 8th International MOS-AK Workshop Washington DC December 9, 2015

 8th International MOS-AK Workshop 
  Washington DC December 9, 2015 
  The Final MOS-AK Workshop Program

 
Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Washington DC in the IEDM / CMC meetings timeframe on December 9, 2015. The MOS-AK workshop is organized with aims to strengthen an academic/industry network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue:    

Embassy of Switzerland
2900 Cathedral Ave, NW,  
Washington, DC 20008 
USA 

Free Online Workshop Registration:

http://www.mos-ak.org/washington_dc_2015/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Workshop Agenda:

• MOS-AK Workshop - Dec, 9, 2015
  
• Online Technical Program http://www.mos-ak.org/washington_dc_2015/
  
• 08:30 - 09:00 - On-site Registration 
  
• 09:00 - 12:30 - Morning MOS-AK Session
• TCAD and Advanced CMOS Technologies
• Compact Modeling and Reliability Co-simulation
• 12:30 - 13:30 - Lunch
• 13:30 - 17:00 - Afternoon MOS-AK Session 
• CMC Compact Model Standardization
• FOSS Tools for Compact Model Verilog-A Standardization
• 17:00 End of the workshop
  

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)

Extended MOS-AK Committee

WG/18/11/15

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[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient

[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015

Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.

Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6

URL / doi: 10.1109/ESSCIRC.2015.7313863