[report] OpenSUSI Open Source Ecosystem in Japan

Jun Okamura

Open Source Ecosystem in Japan, New OSS Design Activities

IEEE Solid-State Circuits Magazine (Winter 2025)

DOI: 10.1109/MSSC.2025.3634946

The Open Source Utilized Silicon Initiatives (OpenSUSI), established in April 2024 as a nonprofit organization, released an open source 1μm CMOS technology document and the original PDK known as TR-1um [1], on its GitHub repository. The technology was provided by TOKAI RIKA Co., Ltd. [2]. Together with platforms such as SkyWater, GlobalFoundries, and IHP, the availability of such alternative device technologies is vital for the global OSS design community.

On 24–25 September 2025, Kyushu University, TOKAI RIKA, OpenSUSI, and ISHI-Kaian OSS design community in Japan, jointly held a hands-on design seminar using the TR-1-μm open source PDK [read more...]

FIG: (a) and (b) The GDSIIs made by the hands-on design seminar at Kyushu University.

References:

[1] "OpenSUSI/TR-1um" GitHub. [Online]. Available: https://github.com/OpenSUSI/TR-1um

[2] "Tokai Rika" Tokai Rika. [Online]. Available: https://www.tokai-rika.co.jp/en/

[3] "Education Center for Semiconductors and Value Creation" Kyushu University. [Online]. Available: https://ecsvc. ed.kyushu-u.ac.jp/en/index.html

[4] "Security camp 2025 national convention | developing digital talent" IPA (Independent Administrative Agency for Information Processing Promotion). [Online]. Available: https://www.ipa.go.jp/jinzai/security-camp/2025/camp/zenkoku/index.html

[5] R. Brown, "Re: Open letter to the openSUSE Board, project and community (final)," openSUSE Mailing Lists, Jul. 15, 2024. [Online]. Available: https://www. opensusi.org/open-letter

[mos-ak] [ICMC 2026] Call for Papers!

Submission Deadline: February 1, 2026

Call for Papers Submission Site Now Open Submit Now Important Dates February 1, 2026: Submission Deadline April 6, 2026: Acceptance Notification May 10, 2026: Final Version for Publication This year, the International Compact Modeling Conference (ICMC) especially encourages submissions in the following domains: Electrostatic Discharge (ESD) modeling for protection design Reliability and aging-aware compact models and simulation techniques AI or Machine Learning for model development, parameter extraction, circuit simulation efficiency, etc. We are also seeking submissions in the following domains: Application of Device Models Device Model Development Model Enhancements and Implementations Emerging Devices Submit Now Conference Sponsors Media Sponsors Industry Sponsors LinkedIn Website Copyright © 2026 Conference Catalysts, LLC, All rights reserved. You are receiving this email because of your interest and/or previous participation in ICMC. Our mailing address is: Conference Catalysts, LLC 2720 NW 6th St Gainesville, FL 32609 Add us to your address book Want to change how you receive these emails? You can update your preferences or unsubscribe from this list. Forward to a Friend

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2026 Asia-Pacific Workshop on Advanced Semiconductor Devices

2026 Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD 2026)

July 12-14, 2026

Asti Hotel Busan, Korea

Paper submission deadline: Apr 19, 2026

This annual workshop has been held alternately in Japan and Korea since 1993, and the AWAD 2026 Workshop will be the 33rd in workshop's series. The purposes of this workshop are to bring scientists and engineers together, actively engaged in advanced semiconductor devices and materials, and to discuss the present and future device processing and related technologies. The workshop will cover the entire field of semiconductor devices and materials, from fundamental physics to recent improvements in device performance and processing technology [read more...] 

[For Korean Participants] AWAD 학회는 BK21 Four 규정에 따른 국제학회입니다.

AWAD 2026 Venue Asti Hotel Busan [48733] 7-8, Jungang-daero 214 beon-gil, Dong-gu, Busan, Republic of Korea Important Dates Paper submission deadline: Apr 19, 2026 Acceptance notification: May , 2026 Author registration: June, 2026 Advance registration: June, 2026

Topics of Interest Advanced semiconductor technologies MOS logic and memory devices Characterization and simulation Quantum devices and computing technologies Compound semiconductor materials and devices Optoelectronics, displays, and imagers Nano, 2D materials, and wearable devices Power electronic devices Neuromorphic devices and compute technologies Advanced packaging technologies

Organized by 

• The Institute of Electronics and Information Engineers (IEIE), Korea 
• The Institute of Electronics, Information and Communication Engineers (IEICE-ES), Japan
• IEEE Electron Devices Society (EDS) Seoul Section Chapter

FETCH2026 Program

FETCH2026

4-6 Février 2026

Lavey-les-Bains (Vaud, Suisse)

Purpose: Mastering the heterogeneity of embedded systems through efficient design technologies is an unavoidable challenge for the years to come. To monitor and anticipate the emergence of new techniques for modelling, validating and synthesising these systems, FETCH 2026 aims to bring together and cross-reference expertise in these various facets. It is a unique annual event for scientists and professionals wishing to share and exchange the most recent knowledge in these fields [read more...]

FETCH2026 Program
Time	Speaker	Affiliation	Title
Feb. 4
08:20	Thoma, Upegui, Levisse	—	Introduction
08:30	David Ruffieux	CH-CSEM	Capteurs intelligents sans fil et énergie autonomes
09:20	Antoine Frappé	FR-JUNIA	Ultra-low-power Human Area Network
09:40	Kevin Martin	FR-Université Bretagne Sud	Splitting embarrassingly parallel loops of tinyML applications
10:00	Pause	—
10:30	Damien Querlioz	FR-Université Paris Sud	Memristors pour une IA de confiance
10:50	Jean‑Michel Portal	FR-AMU Marseille	TBD
11:10	Cédric Marchand	FR-EC Lyon	Transistors ferroélectriques & PUF
11:30	Laura Begon‑Lours	CH-ETHZ	Oxydes ferroélectriques pour circuits neuromorphiques
11:50	Repas	—
13:20	Benoit Miramond	FR-Université Côte d’Azur	From Spikes to Silicon
14:10	Eric Fragnière	CH-HEIA‑FR	Implémentation analogique intégrée de SNN
14:30	Léopold Van Brandt	BE-UCL	Excitabilité des neurones à impulsions
14:50	Ma thèse en 180s	—
15:40	Posters / Pause	—
16:25	Jérôme Toublanc	FR-Synopsys	Implémentation multiphysique des semi‑conducteurs
16:45	Bertrand Reulet	CA-Université Sherbrooke	Bruit d’un système non‑linéaire
17:05	Andreas Burg	CH-EPFL	Fin du CMOS SRAM scaling
17:25	Dragomir Milojevic	BE-Université Libre de Bruxelles	3D stacking & CMOS2.0
20:00	Repas	—
Feb. 5
08:30	Jean‑Paul Chaput	FR-LIP6	Coriolis: RTL→GDSII
09:20	Cesar Fuguet	FR-INRIA	Cost of ECC in RISC‑V L1
09:40	Christian Fabre	FR-CEA	RISC‑V, open hardware & open source
10:00	Pause	—
10:30	Sylvain Saïghi	FR-IMS Bordeaux	EU RadioSpin
10:50	Agathe Archet	FR-Thales	HW‑NAS for heterogeneous embedded targets
11:10	David Novo	FR-LIRMM	Systolic arrays for ADAM Edge AI
11:30	Martin Andraud	BE-Université catholique de Louvain	Test & reliability in analog AI accelerators
11:50	Alberto Dassatti	CH-HEIG‑VD	Democratizing NVMe storage research
12:10	Repas	—
13:40	Paolo Maistri	FR-Université Grenoble	Effets des rayons X sur FPGA sécurisés
14:00	Olivier Savry	FR-CEA	Intégrité de calculs processeurs
14:20	Pascal Cotret	FR-ENSTA	Enclave‑aware cache replacement
14:40	Ma thèse en 180 s	—
15:30	Posters / Pause	—
16:20	Thomas Bourgeat	CH-EPFL	Verified OoO execution in dataflow circuits
16:40	Laurent Maillet‑Contoz	FR-STMicroelectronics	Jumeaux numériques
17:00	Laurence Pierre	FR-TIMA	Vérification d’émulation RISC‑V dans QEMU
20:00	Repas	—
Feb. 6
08:30	Benoit Larras	FR-JUNIA	Event‑driven binarized conv layer
08:50	Marina Reyboz	FR-CEA	TBD
09:10	Bertrand Granado	FR-Sorbonne Université	IA médicale & explicabilité
09:30	Ranwa Al Mallah	CA-Collège militaire royal du Canada	Robustesse RL embarqué face aux attaques
09:50	Fatma Jebali	FR-CEA	AI‑driven performance modeling
10:10	Pause	—
10:40	Anna Sfyrla	CH-UNIGE / CERN	FPGAs & Higgs boson
11:30	Quentin Berthet	CH-HEPIA	Accélération du trigger ATLAS
11:50	Felipe Magalhaes	CA-Polytechnique Montréal	Systèmes temps réel partitionnés
12:10	Sébastien Roy	CA-Université de Sherbrooke	ColdHive IoT platform
12:30	Mot de la fin	—
12:40	Repas	—

[Review] Organic Transistors Compact Models

Monideepa Dutta, Nikhil Ranjan Das, Benjamin Iñiguez, Alexander Kloes, Ghader Darbandy

Review of DC and AC Core Compact Models and Device Performance in Organic Transistors 

J. Appl. Phys. 139, 010701 (2026 Open Access)

DOI: 10.1063/5.0303946

1. NanoP, TH Mittelhessen University of Applied Sciences, 35390 Gießen (D)

2. Institute of Radio Physics and Electronics, University of Calcutta, West Bengal (IN)

3. Department of Electronic Engineering, Universitat Rovira i Virgili, 43007 Tarragona (SP)

Abstract: Organic transistors offer lightweight, flexible, and low-cost platforms for large-area electronics, making them particularly attractive for applications in wearables and biosensing. Their effective use requires detailed characterization and accurate simulation, with compact models providing the foundation for predicting device behavior and enabling reliable circuit-level design. Yet, the diversity of organic semiconductors and the complexity of charge transport demand multiple core modeling approaches, each built on distinct physical assumptions. First, this review summarizes reported lateral and vertical organic transistor architectures, outlining their structural principles and material implementations. It then considers core compact physics-based models for both DC and AC operation, emphasizing their formulations, underlying assumptions, and the physical effects they incorporate. Finally, it reviews reported DC and AC characteristics across diverse material systems, with particular attention to bias-normalized parameters that enable consistent and meaningful cross-study comparisons. By exploring existing core models and performance analyses, this review highlights the fundamental physical principles incorporated into reported compact models and bridges device-level physics with application-oriented circuit design. It offers a comparative perspective on modeling strategies suitable for flexible and biointegrated electronics, while identifying key overlaps in the literature and providing a foundational framework for efficient future model development. Additionally, the review underscores the importance of harmonized terminology to accelerate the development of next-generation models and enhance consistency across studies.

Fig : Virtual-source point x0 in the channel, where the carrier charge and velocity are defined, corresponding to the peak of the conduction band profile.

Acknowledgments : The authors would like to acknowledge the funding from the German Research Foundation (DFG) under Grant Nos. “DA 2578/2-1” and “INST169/22-1.”