[paper] 60GHz Class-AB PA in 22nm FD-SOI CMOS

Dimitrios Georgakopoulos, Vasileios Manouras and Ioannis Papananos

A 60-GHz Current Combining Class-AB Power Amplifier in 22 nm FD-SOI CMOS

Microwave 2026, 2(1), 2; DOI: 10.3390/microwave2010002

* School of Electrical and Computer Engineering, National Technical University of Athens, (GR)

Abstract: This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ( 𝑃𝑠𝑎𝑡 ) of 20.2 dBm, and a maximum large-signal gain (𝐺𝑚𝑎𝑥 ) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes. 

FIG: Top-level schematic of the overall mm-Wave PA, including layout of all passive networks

[paper] Compact IV Model for DG MoS2 FETs

Ahmed Mounir, Francois Lime, Alexander Kloes, Alexandros Provias, Theresia Knobloch, 

K. P. O’Brien, Tibor Grasser and Benjamin Iniguez

Compact I–V Model for Double-Gated MoS2 FETs Including Short-Channel Effects

IEEE TED, Vol. 72, No. 12, Dec 2025

DOI: 10.1109/TED.2025.3622099

Rovira i Virgili University, Tarragona (SP)
THM University of Applied Sciences, Giessen (D)
Technical University of Vienna (A)
Intel Foundry Technology Research, Hillsboro (US)

Abstract: This article presents a physics-based analytical compact model for double-gated molybdenum disulfide (MoS2) field effect transistors (FETs), incorporating key physical and short-channel effects (SCEs), such as mobility degradation and velocity saturation. The model is developed from a unified charge control model by evaluating the charge density within the 2D MoS2 layer, represented using the Lambert W function, which provides an analytical expression valid and continuous from the subthreshold to the above threshold regime. The drain current is then derived from this unified charge control model, and as a function of closed-form equations for the charge densities at the source and drain ends of the channel. Despite its simplicity, the model shows excellent agreement with experimental data for channel lengths down to 60nm, making it a powerful tool for accurately predicting the performance of downscaled devices. By including SCEs, this work extends previous modeling efforts and provides a more comprehensive framework for the simulation and optimization of 2D material-based FETs in circuit design.

FIG: Cross-sectional view of the double-gated MoS2 FET, showing the top gate oxide stack made of Al2O3 and HfO2, with the local back gate oxide consisting of HfO2. Validation of the compact model against experimental data for double-gate MoS2 FET L = 60nm (bottom line)

Acknowledgements: This work was supported in part by European Union Bayesian inference with flexible electronics for biomedical applications (BAYFLEX) under Contract 101099555 and in part by the Ministry of Science of Spain under Contract PID2021122399OB-I00

[book] CMOS RF and mm-Wave Transceivers and Synthesizers

CMOS RF and mm-Wave Transceivers and Synthesizers

(1st ed. 2025)

By Bharatha Kumar Thangarasu, Nagarajan Mahalingam, 

Kaixue Ma, Kiat Seng Yeo

Jenny Stanford Publishing

DOI 10.1201/9781003673569

Abstract: Power consumption has become a critical concern in RF/mm-wave integrated circuit (IC) design thanks to new applications from 5G, mobile computing, artificial intelligence, and the Internet of Things. However, big challenges lie ahead for chip designers when they choose to develop ICs using silicon technology for low-power and high-data-rate applications. This is because silicon technology suffers from undesirable energy dissipation due to its lossy substrate and high resistive wiring loss at GHz frequencies. Nonetheless, silicon remains the most suitable material, satisfying the demands of a rapidly growing semiconductor market through low fabrication cost and ease of achieving system-on-chip or system-in-package integration. While long being neglected, low-power RF/mm-wave design has vaulted to the forefront of attention in recent years due to the demand for ultra-low-power transceivers to achieve sustainability. Designing genuinely ubiquitous transceivers for these new applications requires innovations in both system architecture and circuit implementation.

This book closes the gap between a typical textbook with theories that are difficult to understand and a design-oriented book that offers little insight into actual theories. It evaluates and discusses different circuit topologies, receiver and transmitter architectures, phase-locked loop performance metrics, phase noise analysis, and sub-system-level designs that have yet to be reported in other books.

Table of Contents

• Chapter 1: CMOS RF Active and Passive Devices (pp. 1–49)
• Chapter 2: Transceiver Building Blocks (pp. 50–126)
• Chapter 3: Receiver Sub-System (pp. 127–193)
• Chapter 4: Transmitter Sub-System (pp. 194–238)
• Chapter 5: Transceiver System Integration (pp. 239–347)
• Chapter 6: CMOS RF/mm-Wave Oscillators (pp. 348–401)
• Chapter 7: CMOS Frequency Synthesizers (pp. 402–482)

[open source hardware] selected examples

 SemiCoLab - Multi-project platform on ASIC

SemiCoLab is an educational project that seeks to democratize the complete integrated circuit design process. It allows students, teachers, and enthusiasts to design digital logic with open-source tools and fabricate it on a multiproject wafer, sharing costs and accelerating hands-on learning.

VSDSquadron Mini - RISC-V Development Kit

The VSDSquadron Mini, a versatile powerhouse within the RISC-V landscape that elevates your development to new heights. Whether you’re a newcomer delving into the realm of embedded systems or an experienced developer crafting an intricate device, the VSDSquadron Mini is your ideal companion. It seamlessly bridges the gap between theory and practical application, offering an on-board flash programmer with single-wire programming protocol to jumpstart your projects in education and development with proficiency and ease.

Watchy - A fully open source & customizable E-Ink watch

Watchy is an E-Ink watch with open source hardware and software. It has a barebones design utilizing the PCB as the watch body, allowing it to be worn as-is, or further customized with different 3D printed cases and watch straps. It is a unique timepiece that is also a wearable development platform, allowing users to create their own experience.

[paper] Open Source EDA Tools in ASICs

Édney M. V. Freitas, Nicolas Guimarães, Rafael Maria, Felipe Costa, 

Guilherme Milani, Bruno Sanchesand, Wilhelmus Van Noije

Using Open Source EDA Tools in ASICs for HEP: A Mixed Comparison

arXiv:2512.06122v1 [hep-ex] 5 Dec 2025

1. Escola Politécnica da Universidade de São Paulo, Brazil

Abstract: This work compares open-source electronic design automation tools with a commercial environment using three representative integrated circuit blocks in the IHP 130nm open PDK: a common-mode noise filter, a finite-state machine, and a voltage-controlled oscillator. The study reports design effort and quality of results for digital logic, including area, power, and timing closure, and examines analog layout feasibility. For the finite-state machine at 50 MHz, the open-source flow reached 0.029 mm2 (post-layout) and 4.37 mW (estimated) with 828 standard cells, whereas the commercial flow achieved 0.019 mm2 and 2.00 mW with 497 cells, corresponding to increases of 53% in area and 118% in power. The common-mode noise filter totals 1.879 mm2 with 1703 flipflops at 50 MHz. The voltage-controlled oscillator occupies 0.0025 mm2 and achieves a simulated maximum oscillation frequency of 2.65 GHz. The contribution is a side-by-side quantification of quality of results across digital and analog blocks in the IHP open PDK. The results indicate that open-source tools are viable for early prototyping, training, and collaboration, while commercial flows retain advantages in automation and quality of results when strict targets on power and area or precision analog layout are required.

FIG: Digital layouts under identical constraints. Layer colors are tool specific.

Acknowledgments: This work was financed, in part, by the São Paulo Research Foundation (FAPESP), Brazil, Grants #2024/04802-9 and #2024/06703-8, by CNPQ Grant #134869/2024-9. This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES), Brazil - Finance Code 001.