[paper] Rapid MOSFET Threshold Voltage Testing

Michael H. Herman; Trenton T. Nguyen; Ken Wong; Jeff Johnson; Ben Morris

Rapid MOSFET Threshold Voltage Testing

for High Throughput Semiconductor Process Monitoring

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS)

Edinburgh, United Kingdom, 2024, pp. 1-6

doi : 10.1109/ICMTS59902.2024.10520252

* Parametric Test Group, Advantest America, San Jose, CA 95134 United States

Abstract : We describe a method for rapid MOSFET threshold voltage (Vt) measurement. Multiple spot Ids measurements are compared to stored reference data. Each spot measurement yields an independent Vt estimate, and these enable quality metric calculation. A Vt and quality metric can be measured within 7 msec, using two spot measurements. The method permits parallel MOS testing.

FIG : Reference Ids-Vgs Curve with Gm curveB2Q8 device 2N7002 NMOS Transistor
at Vds = 0.05 Gm(max) 0.02272 at Vgs 2.25V; Extrap tangent line at 1.8665V

[paper] CMOS strip sensors

Naomi Davis a, Jan-Hendrik Arling a, Marta Baselga d, Leena Diehl b f, Jochen Dingfelder c, Ingrid-Maria Gregor a, Marc Hauser b, Fabian Hügging c, Tomasz Hemperek c h, Karl Jakobs b, Michael Karagounis e, Roland Koppenhöfer b, Kevin Kröninger d, Fabian Lex b, Ulrich Parzefall b, Arturo Rodriguez b g, Birkan Sari d, Niels Sorgenfrei b f, Simon Spannagel a, Dennis Sperlich b, Tianyang Wang c, Jens Weingarten d, Iveta Zatocilova b

Characterisation and simulation of stitched CMOS strip sensors

Nuclear Instruments and Methods in Physics Research Section A:

Accelerators, Spectrometers, Detectors and Associated Equipment

Volume 1064, July 2024, 169407

DOI: 10.1016/j.nima.2024.169407

a Deutsches Elektronen Synchrotron DESY, Notkestr. 85, 22607 Hamburg, Germany
b Physikalisches Institut, University of Freiburg, Hermann-Herder-Straße 3, 79104 Freiburg, Germany
c Physikalisches Institut, University of Bonn, Nussallee 12, 53115 Bonn, Germany
d Physik E4, TU Dortmund, Otto-Hahn-Strasse 4a, 44227 Dortmund, Germany
e Fachhochschule Dortmund, Sonnenstraße 96, 44139 Dortmund, Germany
f CERN, Esplanade des Particules 1, 1211 Meyrin, Switzerland
g Littlefuse, Edisonstraße 15, 68623 Lampertheim, Germany
h DECTRIS AG, Täfernweg 1, 5405 Baden, Switzerland

Abstract : In high-energy physics, there is a need to investigate alternative silicon sensor concepts that offer cost-efficient, large-area coverage. Sensors based on CMOS imaging technology present such a silicon sensor concept for tracking detectors. The CMOS Strips project investigates passive CMOS strip sensors fabricated by LFoundry in a 150 nm technology. By employing the technique of stitching, two different strip sensor formats have been realised. The sensor performance is characterised based on measurements at the DESY II Test Beam Facility. The sensor response was simulated utilising Monte Carlo methods and electric fields provided by TCAD device simulations. This study shows that employing the stitching technique does not affect the hit detection efficiency. A first look at the electric field within the sensor and its impact on generated charge carriers is being discussed.

Fig : Schematic layout of the Regular (a) and Low Dose 30/55 (b) strip implant designs 

Acknowledgements : The measurements leading to these results have been performed at the Test Beam Facility at DESY Hamburg (Germany), a member of the Helmholtz Association (HGF).

[paper] Insights from Basilisk

Philippe Sauter∗, Thomas Benz∗, Paul Scheffler∗ , Frank K. Gurkaynak∗ , Luca Benini∗†

Insights from Basilisk:

Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?

arXiv:2405.04257v2 [cs.AR] 8 May 2024

* Integrated Systems Laboratory, ETH Zurich, Switzerland
† Department of Electrical, Electronic, and Information Engineering, University of Bologna, Italy

Abstract: Designing complex, multi-million-gate application specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-onchip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP’s open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3 improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6. Furthermore, tool runtime was reduced by 2.5, and peak RAM usage decreased by 2.9. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.

FIG: Layout files produced by running the original Iguana flow (a) and of Basilisk (b).

TABLE: KEY METRICS OF BASILISK

Logic area (NAND2)	1.1 MGE
Logic levelsa	51 LL
Technology	130 nm IHP
Operating frequency	77 MHz
SRAM memory	172 KiB (24 macros)
Chip / core area	39 mm / 21 mm
IO count	69

^aNumber of logic gates in the longest path

Acknowledgement: We thank Alan Mishchenko, Masahiro Fujita, Giovanni De Micheli, Andrea Costamagna, Alessandro Tempia Calvino, Osama Hammad Abdel Reheem, Matt Liberty, Martin Poviser, the Yosys team, Beat Muheim, and Zerun Jiang, for their valuable contributions to the research project. We further thank all contributors to the OS EDA tools.

We are deeply grateful to IHP for their generous support and providing us with the opportunity for an open-source tapeout of this scale.
This work was supported in part through the TRISTAN (101095947) project that received funding from the HORIZON KDT-JU programme

OSOC Initiative

One Student One Chip Initiative

Participators: Frontier System Laboratory, Architecture Laboratory

Status: Ongoing

The OSOC project guides students to design a tape-out open-source processor by combing EE with CS. It can help students improve their capacity of implementing software and hardware systems and learn how to design chips. Meanwhile, the project trains talents to be transferred to the high-performance processor "Xiangshan", open source EDA, open source IP and other teams and communities, which will continue to cultivate excellent reserve forces for advanced research and development of CS in China.

REF:

Institute of Computing Technology, Chinese Academy of Science　

No.6 Kexueyuan South Road Zhongguancun, Haidian District Beijing,China　

<https://acs.ict.ac.cn/english/projects_acs_en/202209/t20220927_46170.html>

[OpenUK] Open Manifesto

https://openuk.uk/openmanifesto/

February 6, 2024, launched at State of Open Con 24

Table of Contents:

1. Introduction

2. The status quo in the UK

3. Problems with the status quo

4. Three asks of a new UK Government

5. Vision: Giving back control through Open Source

6. Key benefits to UK economy by giving back control through Open Source

https://openuk.uk/stateofopen/