Apr 15, 2024

[course] MEAD @ EPFL

Live Course @ EPFL, Lausanne, Switzerland
JUNE 17-21, 2024

Registration Deadline: May 17, 2024 >> REGISTER

MONDAY, June 17

8:30 am-12:00 pmMOS Transistor Modeling for Low-Voltage and Low-Power Circuit DesignChristian Enz
1:30-5:00 pmDesign of Low-Power Analog Circuits using the Inversion CoefficientChristian Enz

TUESDAY, June 18

8:30 am-12:00 pmNoise Performance of Elementary Circuit BlocksBoris Murmann
1:30-5:00 pmOpamp Topologies and Design FundamentalsBoris Murmann

WEDNESDAY, June 19

8:30-10:00 amLow-Power High Efficiency OpAmp DesignKlaas Bult
10:30 am-12:00 pmLow-Power High Efficiency Residue AmplifiersKlaas Bult
1:30-3:00 pmAnalog Design Methodology and Practical Techniques for Frequency CompensationVadim Ivanov
3:30-5:00 pmEnergy Efficient Voltage References, Biasing in Analog Systems and Current SourcesVadim Ivanov

THURSDAY, June 20

8:30-10:00 amPower Dissipation in ADC Buidling BlocksKlaas Bult
10:30 am-12:00 pmPower Dissipation in ADCsKlaas Bult
1:30-5:00 pmMicropower ADCsKofi Makinwa

FRIDAY, June 21

8:30 am-12:00 pmEnergy Efficient Sensor InterfacesTaekwang Jang
1:30-5:00 pmLow-Power Frequency Reference CircuitsTaekwang Jang
1:30-5:00 pmPower Management With Nanoampere Consumption and Efficient Energy HarvestingVadim Ivanov

Apr 14, 2024

GDR SOC2 IEEE CASS

GDR SOC2 - IEEE CASS
“Tour de France” - Grenoble - 19 April 2024
Open Hardware: the new road?
INP; 46 Av Felix Viallet 38000 Grenoble – Amphi Gosse

8:30  Prof. Boris Murmann (U. of Hawaii) 
Re-Energizing Analog Design using the Open-Source Ecosystem. 
9:30  Aurélien Nicolet (CIME-P)
The French platform supporting open hardware
10:00 Krzysztof Herman (IHP)
 IHP Open Source PDK -  sharing experience after one year of development.
11:00 75th anniversary of CAS Society Keynote by Prof. Ricardo Reis.
12:00 Lunch & Cocktail
14:00 Prof. Ricardo Reis (UFRGS)
 Why joining IEEE CAS Society?
14:30 Jean-Paul Chaput (LIP6 – Sorbonne University)
 Coriolis, The European Open Hardware Project 
15:30 Dr. Leonardo Gomes (TIMA - UGA)
 The first 60 GHz circuit designed with open hardware platform
16:00 Deni Alves (UFSC)
 ACM, a design-oriented model for open tools

Inscription Gratuite: à laurence.ben-tito@univ-grenoble-alpes.fr  








Apr 12, 2024

[paper] Heterojunction Nano-HEMT

G. Purna Chandra Rao1, Trupti Ranjan Lenka2, Valeria Vadalà3
and Hieu Pham Trung Nguyen4
Characteristics Study of Heterojunction III-Nitride/β-Ga2O3 Nano-HEMT for THz Applications
Eng. Res. Express (2024) in press
DOI: 10.1088/2631-8695/ad3db1

1 Electronics and Communication Engineering, NIT Silchar, Assam (IN)
2 Electronics and Communication Engineering, NIT Silchar, Assam (IN)
3 Physics, University of Milan-Bicocca (IT)
4 Electrical and Computer Engineering, Texas Tech University (USA)

Abstract: In this research study, a recessed gate III-Nitride high electron mobility transistor (HEMT) grown on a lattice matched β-Ga2O3 substrate is designed. This research investigation aims to enhance DC and RF performance of AlGaN/GaN HEMT, and minimize the short-channel effects by incorporating an AlGaN back layer and field plate technique, which can enhances electron confinement in two-dimensional electron gas (2DEG). A precise comparison analysis is done on the proposed HEMT’s input characteristics, output characteristics, leakage current characteristics, breakdown voltage properties, and RF behaviour in presence and absence of AlGaN back layer in regard to field plate configuration. The inclusion of back barrier aids in raising the level of conduction band, which reduces leakage loss beneath the buffer, and aids in keeping the 2DEG to be confined to a narrow channel. Furthermore, the field plate design offers an essential electric field drift between gate and drain, resulting to enhanced breakdown voltage characteristics.
FIG : Epitaxial schematic illustration of suggested III-nitride HEMT with the proposed back barrier and field plates.

Acknowledgment : The authors acknowledge SERB (Science and Engineering Research Board), Govt. of India sponsored Mathematical Research Impact Centric Support (MATRICS) project no. MTR/2021/000370 for support.



Apr 8, 2024

[Symposium] SFRC AIST

Advanced Semiconductor Research Center (SFRC) 
National Institute of Advanced Industrial Science and Technology (AIST)
1st Open Symposium 
https://unit.aist.go.jp/sfrc/sfrcsympo202405.html

Date: May 27, 2024
Venue: Fujisoft Akiba Plaza Akiba Hall (3 Kanda-Neribaki-cho, Chiyoda-ku, Tokyo) 
Hybrid event (on-site participation and remote streaming)

AGENDA:
Moderator: Takashi Matsukawa (Deputy Director, SFRC)
13:00-13:05 Opening Remarks Tetsuji Yasuda (AIST Electronics & Manufacturing)
13:05-13:10 Guest Greetings Mr. Tsutomu Kanashi (Director, Information Industry Division, Commerce and Information Policy Bureau, Ministry of Economy, Trade and Industry)
13:10-13:40 Keynote Speech 1 "Rapidus and Advanced Semiconductor Development" Masaharu Kobayashi (Rapidus Corporation)
13:40-14:10 Keynote Speech 2 "The Current Situation and Future of the Semiconductor Industry from a Systems Perspective" Kenji Tsuda (International Technology Journalist)
14:10-14:20 "Introduction to the Advanced Semiconductor Research Center" Akiue Masahara (Director, SFRC Research Center)
14:20-14:40 "Introduction of SCR Open Pilot Line" Fuminori Ito (Deputy Director, SFRC)
14:40-14:55 "2nm Generation GAA-FET Fundamental Technology" Hisashi Irizawa (SFRC) Head, Device Process Research Team)
14:55-15:10 "Extreme Device and Material Technology for the 2nm Generation and Beyond" Naoya Okada (Head, Extreme CMOS Materials Research Team, SFRC)
15:10-15:30 Coffee Break
15:30-16:00 Keynote Speech 3 "What is Open Source Utilized Silicon Initiatives (Open-SUSI)?" Jun-Ichi Okamura (AIST Solutions)
16:00-16:15 "Device Integration Technology by 3D Integrated Packaging Technology Katsuya Kikuchi (Director, SFRC 3D Integrated Technology Research Team)
16:15-16:30 "Advanced System-on-Chip (SoC) Design Technology"
Shinichi Ouchi (AIDL Laboratory Team Leader/SFRC Integrated Circuit Design Research Team)
16:30-16:45 Environmental Impact Assessment of Semiconductor Manufacturing and Greening Technologies" Shinji Mimida (SFRC)
16:45-17:00 "Quantum-related semiconductor integrated device technology" Takahiro Mori (Director, SFRC New Principles Silicon Device Research Team)
17:00-17:15 Q&A
17:15-17:30 Closing Remarks Takashi Nakano (Deputy Director, Research Strategy Planning Department, AIST)

On-site participation, remote participation: Participation is free. (Please register for this form) Remote streaming is scheduled for Zoom. Please register one by one if you wish to participate. Please note that there is a limit to the number of participants at the venue.

Secretariat contact <https://unit.aist.go.jp/sfrc/sfrcsympo202405.html>
National Institute of Advanced Industrial Science and Technology (AIST) Advanced Semiconductor Research Center Symposium Secretariat (M-SFRC-Sympo-ml@aist.go.jp)

Apr 5, 2024

[paper] Organic Electrochemical Transistor Arrays

Jaehyun Kim, Robert M. Pankow, Yongjoon Cho, Isaiah D. Duplessis, Fei Qin, Dilara Meli, Rachel Daso, Ding Zheng, Wei Huang, Jonathan Rivnay, Tobin J. Marks and Antonio Facchetti
Monolithically integrated high-density vertical organic electrochemical transistor arrays
and complementary circuits.
Nat Electron 7, 234–243 (2024)
DOI: 10.1038/s41928-024-01127-x

1 Department of Chemistry and Materials Research Center, Northwestern University, Evanston, IL, USA
2 Department of Semiconductor Science, Dongguk University, Seoul, Republic of Korea
3 Department of Materials Science and Engineering, Northwestern University, Evanston, IL, USA
4 Department of Biomedical Engineering, Northwestern University, Evanston, IL, USA
5 Laboratory of Organic Electronics, Department of Science and Technology, Linköping University, Sweden
6 School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA, USA


Abstract Organic electrochemical transistors (OECTs) can be used to create biosensors, wearable devices and neuromorphic systems. However, restrictions in the micro- and nanopatterning of organic semiconductors, as well as topological irregularities, often limit their use in monolithically integrated circuits. Here we show that the micropatterning of organic semiconductors by electron-beam exposure can be used to create high-density (up to around 7.2 million OECTs per cm2) and mechanically flexible vertical OECT arrays and circuits. The energetic electrons convert the semiconductor exposed area to an electronic insulator while retaining ionic conductivity and topological continuity with the redox-active unexposed areas essential for monolithic integration. The resulting p- and n-type vertical OECT active-matrix arrays exhibit transconductances of 0.08–1.7 S, transient times of less than 100 μs and stable switching properties of more than 100,000 cycles. We also fabricate vertically stacked complementary logic circuits, including NOT, NAND and NOR gates.
FIG: High-density monolithically integrated vOECT arrays fabricated by e-beam exposure.
 a.) Photograph  vOECT arrays comprising bgDPP-g2T OECTs
b.) Transconductance map of the wafer-scale vOECTs; 
c.) Transfer IVs of 100 bgDPP-g2T vOECTs (W = d = 10 µm) 

Acknowledgements: This work was supported by the AFOSR (contract no. FA9550-22-1-0423), the US Office of Naval Research Contract no. N00014-20-1-2116, by the US Department of Commerce, National Institute of Standards and Technology as part of the Centre for Hierarchical Materials Design Award no. 70NANB10H005, BSF (award no. 2020384), NSF (DMR-2223922) and the Northwestern University Materials Research Science and Engineering Center Awards NSF DMR-1720139 and DMR-2308691. J.R. gratefully acknowledges support from the Alfred P. Sloan Foundation (FG-2019-12046). This work acknowledges the US Department of Energy under contract no. DE-AC02-05CH11231 at beamline 8-ID-E of the Advanced Photon Source, a US Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. This work made use of the NUFAB facility of Northwestern University’s NUANCE Center, which has received support from the SHyNE Resource (NSF ECCS-2025633), the IIN and Northwestern’s MRSEC programme (NSF DMR-1720139).