IEEE 5NANO2024 Conference 25-26th April, 2024

IEEE 5NANO2024

2024 IEEE International Conference on Nanoelectronics, Nanophotonics,
Nanomaterials, Nanobioscience & Nanotechnology

25th & 26th April 2024

VISAT Engineering College

Elanji, Ernakulam, Kerala, India - 686 665.

The IEEE 5NANO2024 International Conference is going to be dynamic and informative as it provides the premier interdisciplinary forum for researchers, practitioners and educators to present and discuss the most recent innovations, trends, practical challenges encountered, and the solutions adopted in the field of Nanotechnology. The theme of the conference is: “Future Challenges and Advanced Innovations in Nanotechnology”

Contact 5NANO2024:

Dr. T.D.Subash, Conference Organizing Chair - 5NANO2024,
VISAT Engineering College,
Elanji, Ernakulam, Kerala, India - 686 665

Tel: +91 9447691397, +91 9486881397.
E-mail: deanresearch@visat.ac.in, tdsubash2007@gmail.com, 5nano2k24@gmail.com

Website: https://www.5nano2024.com

[paper] in-memory computing using FeFET

Taha Soliman, Swetaki Chatterjee, Nellie Laleni, Franz Müller, Tobias Kirchner, Norbert Wehn, Thomas Kämpfe, Yogesh Singh Chauhan and Hussam Amrouch

First demonstration of in-memory computing crossbar using multi-level Cell FeFET

Nat Commun 14, 6348 (2023)

DOI: 10.1038/s41467-023-42110-y

1 Robert Bosch GmbH, Renningen, Germany
2 Semiconducture Test and Reliability, University of Stuttgart, Stuttgart, Germany
3 Department of Electrical Engineering, IIK, Kanpur, India
4 Fraunhofer IPMS, Dresden, Germany
5 RPTU Kaiserslautern-Landau, Kaiserslautern, Germany
6 MIRMI; Technical University of Munich, Germany

Abstract: Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level ferroelectric field-effect transistor (FeFET) cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based FeFET devices. Unlike traditional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6% accuracy for handwriting recognition and 91.5% accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achieving 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional structural overhead.

FIG: a.) The material stack of FeFETs. 

b.) The multi-bit FeFET can be programmed to different states

to store the weight of the synapse

Acknowledgements: This work has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 826655 and No 876925. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Belgium, France, Germany, Portugal, Spain, The Netherlands, Switzerland. Open Access funding enabled and organized by Projekt DEAL.

[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

SSCS April Technical Webinar

SSCS April Technical Webinar

Getting Started with Open Source Silicon, Presented By: Matthew Venn

Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:

• https://zerotoasiccourse.com/
• https://tinytapeout.com

Date: 2024-04-19 Time: 11 AM ET

Location Webinar - Online

Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

[paper] Topological Transistor Compact Model

Md. Mazharul Islam¹, Shamiul Alam¹, Md. Shafayat Hossain², Ahmedullah Aziz¹

Compact Model of a Topological Transistor

 IEEE Access; Feb.7, 2024

DOI: 10.1109/ACCESS.2024.3363645

1 Department of Electrical Engineering and Computer Science, The University of Tennessee, USA
2 Department of Physics, Princeton University, USA

Abstract: The precession of a ferromagnet leads to the injection of spin current and heat into an adjacent non-magnetic material. Besides, spin-orbit entanglement causes an additional charge current injection. Such a device has been recently proposed where a quantum-spin hall insulator (QSHI) in proximity to a ferromagnetic insulator (FI) and superconductor (SC) leads to the pumping of charge, spin, and heat. Here we build a circuit-compatible Verilog-A-based compact model for the QSHI-FI-SC device capable of generating two topologically robust modes enabling the device operation. Our model also captures the dependence on the ferromagnetic precision, drain voltage, and temperature with an excellent (>99%) accuracy.

FIG: (a) The proposed device structure. A QSHI in proximity with the FI with a monodomain magnetization m(t) that precesses at an angle θ. In proximity to the FI region there is a SC region The monodomain magnetization m(t) precesses at an angle θ around the axis perpendicular to the QSHI. The QSHI region injects charge, spin, and heat currents to the drain. The injection can be controlled by the applied potential at the FI region (Vg), the precession angle (θ), precession frequency (ω) temperature (T) and drain voltage (Vd ). Zero energy Majorana Fermion (MF) is harbored in the FI-SC interface that controls the pumped currents. (b) Circuit schematics for our simulation process. (c) Methodology flow for compact modeling

Acknowledgement: This work was supported by the Air Force Research Laboratory under Agreement FA8750-21-1-1018.