[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

SSCS April Technical Webinar

SSCS April Technical Webinar

Getting Started with Open Source Silicon, Presented By: Matthew Venn

Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:

• https://zerotoasiccourse.com/
• https://tinytapeout.com

Date: 2024-04-19 Time: 11 AM ET

Location Webinar - Online

Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

[paper] Topological Transistor Compact Model

Md. Mazharul Islam¹, Shamiul Alam¹, Md. Shafayat Hossain², Ahmedullah Aziz¹

Compact Model of a Topological Transistor

 IEEE Access; Feb.7, 2024

DOI: 10.1109/ACCESS.2024.3363645

1 Department of Electrical Engineering and Computer Science, The University of Tennessee, USA
2 Department of Physics, Princeton University, USA

Abstract: The precession of a ferromagnet leads to the injection of spin current and heat into an adjacent non-magnetic material. Besides, spin-orbit entanglement causes an additional charge current injection. Such a device has been recently proposed where a quantum-spin hall insulator (QSHI) in proximity to a ferromagnetic insulator (FI) and superconductor (SC) leads to the pumping of charge, spin, and heat. Here we build a circuit-compatible Verilog-A-based compact model for the QSHI-FI-SC device capable of generating two topologically robust modes enabling the device operation. Our model also captures the dependence on the ferromagnetic precision, drain voltage, and temperature with an excellent (>99%) accuracy.

FIG: (a) The proposed device structure. A QSHI in proximity with the FI with a monodomain magnetization m(t) that precesses at an angle θ. In proximity to the FI region there is a SC region The monodomain magnetization m(t) precesses at an angle θ around the axis perpendicular to the QSHI. The QSHI region injects charge, spin, and heat currents to the drain. The injection can be controlled by the applied potential at the FI region (Vg), the precession angle (θ), precession frequency (ω) temperature (T) and drain voltage (Vd ). Zero energy Majorana Fermion (MF) is harbored in the FI-SC interface that controls the pumped currents. (b) Circuit schematics for our simulation process. (c) Methodology flow for compact modeling

Acknowledgement: This work was supported by the Air Force Research Laboratory under Agreement FA8750-21-1-1018.

[paper] Next Wave for AI/ML in Physical Design

Andrew B. Kahng

Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design

ISPD ’24 Proceedings

March 12–15, 2024, Taipei, Taiwan.

DOI 10.1145/3626184.3635277

Abstract: It has been six years since an ISPD-2018 invited talk on “Machine Learning Applications in Physical Design”. Since then, despite considerable activity across both academia and industry, many R&D targets remain open. At the same time, there is now clearer understanding of where AI/ML can and cannot (yet) move the needle in physical design, as well as some of the difficult blockers and technical challenges that lie ahead. Some futures for AI/ML-boosted physical design are visible across solvers, engines, tools and flows and in contexts that span generative AI, the modeling of “magic” handoffs at flow interstices, academic research infrastructure, and the culture of benchmarking and open-source EDA.

Fig: OpenROAD as a new EDA playground for ML researchers

Acknowledgments: Many thanks to Sayak Kundu, Bodhisatta Pramanik, Zhiang Wang and Dooseok Yoon for their help with the figures and text in this paper. Discussions with Siddhartha Nath, Igor Markov, Chuck Alpert and Ilgweon Kang are also gratefully acknowledged. Research at UCSD is partially supported by DARPA, Samsung, the C-DEN center, and gifts from Google, Intel and others.

Importance of Open-Source EDA Tools for Academia

Importance of Open-Source EDA Tools for Academia

Open Letter on European Strategic and Funding Directions

https://open-source-eda-letter.eu/

Initial Signatories of the Open-Source-EDA-Letter, as of March 8, 2024, are:

Luca Benini
University of Bologna, Italy & ETH Zürich, Switzerland
Professor, Lead of the RISC-V PULP platform

Giovanni De Micheli
EPFL Lausanne, Switzerland
Professor and Director, LSI lab

Marie-Minerve Louërat
Sorbonne University, France

Research Scientist, Coriolis Foundation hosted by CNRS Foundation

Harald Pretl
Johannes Kepler University Linz, Austria
Professor, Maintainer of IIC-OSIC-TOOLS

Stefan Wallentowitz
Hochschule München University of Applied Sciences, Germany
Professor, Director at FOSSi Foundation & Director at RISC-V

All the educators and researchers from European academic institutions are kindly asked to consider and eventually co-sign this open letter. To co-sign, please send a mail from your university mailing address to stefan.wallentowitz@hm.edu and include your affiliation and ideally include a link to your profile.