[Open PDK] IEEE EDS DL at IISc Banglare

IEEE EDS/SSCS Bangalore Chapter Presents DL Series

FOSS TCAD/EDA Tools SPICE and Verilog-A

Modeling Flow Technology - Devices - Applications

W.Grabinski, MOS-AK (EU)

DATE AND TIME	LOCATION	HOSTS
Date: 07 Mar 2024 Time: 04:00 PM to 05:00 PM All times are (UTC+05:30) Chennai Add Event to Calendar iCal Google Calendar	Auditorium, Dept. of ESE, IISc Bangalore Karnataka India 560012	Bangalore Section Jt. Chapter ED15/SSC37

[EDTM] Open PDK Initiative

8th IEEE EDTM

March 3-6, 2024

Strengthening Globalization in Semiconductors

The EDTM Conference to host two contributions discussing the status of Open PDK Initiative:

[6C-1] [Invited] Disrupting Conventional Chip Design through the Open Source EDA Ecosystem
Mehdi Saligane; University of Michigan, USA

[P2-36] FOSS CAD for the Compact Verilog-A Model Standardization in Open PDKs
Wladek Grabinski, et al. MOS-AK (EU); IHP - Leibniz-Insitut für innovative Mikroelektronik;

as of March 12, 2024:

 

[EDTM] Inauguration Session

8th IEEE EDTM

March 3-6, 2024

Strengthening Globalization in Semiconductors

The 8th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2024) will be held for the first time in India at Bangalore; the Silicon Valley of India and the hub of semiconductor companies. IEEE EDTM 2024 will be a full four-day conference to be held during March 3-6, 2024. IEEE EDTM 2024 aims to be a premier global forum for researchers and engineers from around the world coming to share new discoveries and discuss any device/manufacturing-related topics, including but not limited to, materials, processes, devices, packaging, modeling, reliability, manufacturing and yield, tools, testing, and any emerging device technologies, as well as workforce training. 

Plenary Talk by Prof. Chenming Hu "Semiconductor – the Next 75 Years?"

[paper] La:HfO2 gate stacked ferroelectric tunnel FET

Neha Paras^a, Shiromani Balmukund Rahi^b, Abhishek Kumar Upadhyay^c,
Manisha Bharti^d, Young Suh Song^e

Design and analysis of novel La:HfO2 gate stacked ferroelectric tunnel FET
for non-volatile memory applications

Memories - Materials, Devices, Circuits and Systems

Volume 7, April 2024, 100101

DOI: 10.1016/j.memori.2024.100101

a Jawaharlal Nehru University, New Delhi, India
b Indian Institute of Technology, Kanpur, India
c X-FAB Dresden GmbH & Co. KG, Dresden, Germany
d National Institute of Technology, Delhi, India
e Korea Military Academy, Seoul, Republic of Korea

Abstract : Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO2) possessing ferroelectric properties. This material is of special interest since it is based on lead-free, simple binary oxide of HfO2, and has excellent endurance property (1 × 109 field cycles without fatigue. There exists substantial information about the material aspects of La:HfO2 but it lacks proven application potential for CMOS-compatible low-power memory design. In this work, 10 % La metal cation fraction of HfO2 (La:HfO2) is proposed as the gate stack material in tunnel FET (TFET) for its potential as a memory device. 2D device simulations are carried out to show that the proposed ferroelectric TFET (FeTFET) provides the largest memory window (MW) as compared to present perovskite ferroelectric materials such as PZT, SBT (SrBi2Ta2O9) and silicon doped (4.6 % Si in HfO2) hafnium oxide (Si:HfO2). The larger window is attributed to greater polarization, and the calculation of MW is quantified by the shift in threshold voltage (Vth). The simulations carried out in this work suggest that La:HfO2 can be adopted as a potential ferroelectric material to target low-power FeTFET design at significantly reduced ferroelectric layer thickness.

FIG: Polarization phenomena of the proposed 

La:HfO2 gate stacked ferroelectric tunnel FET

[FOSSDEM 2024] Open PDK Initiative

FOSDEM 2024 was a two-day event organized by volunteers to promote the widespread use of free and open source software. Took place at the ULB Solbosch campus in the beautiful city of Brussels (Belgium), FOSDEM is widely recognized as the best FOSS conference in Europe.

There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:

• Libre-SOC, FPGA and VLSI DevRoom
• Verilog-AMS in Gnucap
• FOSS CAD/EDA tools supporting the open access PDK initiative
• Open Hardware and CAD/CAM DevRoom
• ngspice circuit simulator - stand-alone and embedded into KiCad

FOSDEM'24 Inauguration Session