[paper] RF NMOS Transistor in a 0.25 µm SiGe-C BiCMOS Process

Engin Cagdas, Huseyin Aniktar, M. Emin Tunbak, Volkan Fenercioglu, 

S. Ebru Arikan, A. Ulvi Caliskan

Modeling and Validation of an Isolated NMOS Transistor

in a 0.25 µm SiGe-C BiCMOS Process

30th IEEE International Conference on Electronics, Circuits and Systems 

(ICECS), Istanbul, Turkiye, 2023, pp. 1-4

DOI: 10.1109/ICECS58634.2023.10382848

*Semiconductor Technologies Research Laboratory, Tübitak Bilgem Yital, Kocaeli, Turkey

Abstract: This study presents the generation of a scalable model based on measurement-aided numerical calculations for INMOS (isolated NMOS) with both PSP and BSIM3 parameter set. Various INMOS structures with several different sizes are fabricated in an in-house developed 0.25 µm BiCMOS process. The validity of the constructed model is verified with the measurement results. This work explains main steps and details of MOS transistor modeling. An RF SPDT switch is also designed with using both PSP and BSIM3 based model. The designed RF SPDT switch performance which is based on these two models is given. Both PSP and BSIM3 model performance are compared in the designed RF SPDT switch simulation results. 

Fig: The INMOS schematic (bottom left): the number 1 represents NMOS transistor, the number 2 Bulk to D-Nwell diode and the number 3 D-Nwell to P-Sub diode. B-4-20 INMOS with DC pad (top left) and with RF pad structure (right). 

Acknowledgment: The authors would like to thank Dr. M. Guntekin Kabuli for valuable discussions and editorial assistance. We would also like to thank the YITAL chip production personel.

DEVSIM as TCAD mobile app

DEVSIM: TCAD mobile app

Now through January 18, 2024, the TCAD app is free for download. After this, you will be entitled to any free future updates [read more...]

• App is renamed to “TCAD app”
• Impact ionization model added
• Menus updated
• Easier plot navigation
• Series resistance available to aid in impact ionization model results
• Stop simulation and keep partial results to stop long-running simulation early

 

[C4P] MIXDES 2024

The MIXDES conference series started in Dębe near Warsaw in 1994 and has been organized yearly in the most interesting Polish cities. In 2024 we would like to continue the tradition of inviting you to the most attractive places in Poland and the conference will take place in Gdańsk between June 27-29, 2024

In short period of time the conference has become an important event in the Central Europe allowing to discuss the recent research progress in the field of design, modelling, simulation, testing and manufacturing in various areas such as micro- and nanoelectronics, semiconductors, sensors, actuators and power devices as well as their interdisciplinary applications.

The topics of the MIXDES 2024 Conference include:

• Design of Integrated Circuits and Microsystems
  Design methodologies. Digital and analog synthesis. Hardware-software co-design. Reconfigurable hardware. Hardware description languages. Intellectual property-based design. Design reuse.
• Thermal Issues in Microelectronics
  Thermal and electro-thermal modelling, simulation methods and tools. Thermal mapping. Thermal protection circuits. 
• Analysis and Modelling of ICs and Microsystems
  Simulation methods and algorithms. Behavioral modelling with VHDL-AMS and other advanced modelling languages. Microsystems modelling. Model reduction. Parameter identification.
• Microelectronics Technology and Packaging
  New microelectronic technologies. Packaging. Sensors and actuators.
• Testing and Reliability
  Design for testability and manufacturability. Measurement instruments and techniques. 
• Power Electronics
  Design, manufacturing, and simulation of power semiconductor devices. Hybrid and monolithic Smart Power circuits. Power integration.
• Signal Processing
  Digital and analogue filters, telecommunication circuits. Neural networks. Artificial intelligence. Fuzzy logic. Low voltage and low power solutions.
• Embedded Systems
  Design, verification and applications.
• Medical Applications
  Medical and biotechnology applications. Biometrics. Thermography in medicine

Call for Papers and Contributions

A call is made for papers, contributions and other conference activities on the topics mentioned above. Full papers should be submitted till March 1, 2024 - only in electronic form (MS Word, RTF, Open Office Writer, LaTeX, together with a generated PDF file).

The paper submission form and required format is available on our Web page. Authors are asked to indicate the topic into which their papers fall. The papers will be reviewed by at least two referees from the International Programme Committee. The papers will be published in the proceedings from the author's electronic submission.

Tutorials and Special Sessions - Call for Proposals

Several tutorials/special sessions will be held prior to the conference. Authors willing to propose a tutorial at MIXDES 2024 are invited to send a proposal to the Organizing Committee. The proposal should consist of a three-page summary including tutorial title, name and affiliation of the lecturer(s), tutorial objectives and audience, topical outline and provisional schedule of the tutorial.

[paper] Neural Compact Modeling Framework

Eom, Seungjoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, and Rock‐Hyun Baek

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Advanced Intelligent Systems (2023): 2300435

DOI: 10.1002/aisy.202300435

Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 37673 (KR)

Abstract: Neural compact models are proposed to simplify device-modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi-device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology-based model parameters using a two-stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (IV) characteristics of the device. Unlike previous neural compact models, this two-stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade-off. The IV characteristics of 1000 amorphous indium–gallium–zinc-oxide thin-film transistor devices with different properties obtained through fully calibrated technology computer-aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

Fig: a) The structure of a-IGZO TFT structure simulated with TCAD

b) Calibrated a-IGZO sub-gap DOS

Acknowledgements: This work was supported in part by the LG Display Company, in part by the Brain Korea 21 Fostering Outstanding Universities for Research (BK21 FOUR) program, in part by Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korea government (MSIT) (grant no. 2019-0-01906, Artificial Intelligence Graduate School Program [POSTECH]), in part by the Ministry of Trade, Industry and Energy (MOTIE) under grant no. 20020265, in part by Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor device, and in part by the Technology Innovation Program (grant no. RS2023-00231985) funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea) (grant no. 1415187390).

[github] new RevEDA Release

Revolution EDA Schematic/Symbol/Layout Editors

https://github.com/eskiyerli/revedaRelease

A new release of Revolution EDA is almost here, including a brand-new hierarchical layout editor with GDS export capability, revamped schematic, and symbol editors. Layout editor can use python-based parametric layout cells. The editor can also create vias and via arrays, paths (Manhattan, diagonal and free-angle), rectangles, polygons, pins and texts. Schematic editor can now import Spice subcircuits and create symbols for inclusion in the schematic editor. A cell can have more than one cellview such as SPICE, Verilog-A or symbol that can be used in the netlisting. The netlisting process can be controlled by a switch-view list or by a separate config view. Unlike leading commercial EDA systems, netlisting and GDS export process are running as separate threads and do not block the user's work.

Any interested parties are kindly invited to get in touch with Murat Eskiyerli, the lead RevEDA developer