Engin Cagdas, Huseyin Aniktar, M. Emin Tunbak, Volkan Fenercioglu,
S. Ebru Arikan, A. Ulvi Caliskan
Modeling and Validation of an Isolated NMOS Transistor
in a 0.25 µm SiGe-C BiCMOS Process
30th IEEE International Conference on Electronics, Circuits and Systems
(ICECS), Istanbul, Turkiye, 2023, pp. 1-4
DOI: 10.1109/ICECS58634.2023.10382848
*Semiconductor Technologies Research Laboratory, Tübitak Bilgem Yital, Kocaeli, Turkey
Abstract: This study presents the generation of a scalable model based on measurement-aided numerical calculations for INMOS (isolated NMOS) with both PSP and BSIM3 parameter set. Various INMOS structures with several different sizes are fabricated in an in-house developed 0.25 µm BiCMOS process. The validity of the constructed model is verified with the measurement results. This work explains main steps and details of MOS transistor modeling. An RF SPDT switch is also designed with using both PSP and BSIM3 based model. The designed RF SPDT switch performance which is based on these two models is given. Both PSP and BSIM3 model performance are compared in the designed RF SPDT switch simulation results.
Fig: The INMOS schematic (bottom left): the number 1 represents NMOS transistor, the number 2 Bulk to D-Nwell diode and the number 3 D-Nwell to P-Sub diode. B-4-20 INMOS with DC pad (top left) and with RF pad structure (right).
Acknowledgment: The authors would like to thank Dr. M. Guntekin Kabuli for valuable discussions and editorial assistance. We would also like to thank the YITAL chip production personel.
