[paper] Boropheneand Metal Interface

Vaishnavi Vishnubhotla, Sanchali Mitra, and Santanu Mahapatraa

First-principles based study of 8-Pmmn boropheneand metal interface

J. Appl. Phys. 134, 034301 (2023); doi: 10.1063/5.0144328

DOI 10.1063/5.0144328

Nano-Scale Device Research Laboratory, Department of Electronic Systems Engineering, 

Indian Institute of Science (IISc) Bangalore, India

Abstract: Borophene, the lightest member of mono-elemental 2D materials family, has attracted much attention due to its intriguing polymorphism. Among many polymorphs, digitally discovered 8-Pmmn stands out owing to its unique tilted-Dirac fermions. However, the property of interfaces between 8-Pmmn and metal substrates has so far remained unexplored, which has critical importance of its application in any electronic devices. Here, with the help of density functional theory, we show that the unique tilted-Dirac property is completely lost when 8-Pmmn borophene is interfaced with common electrode materials such as Au, Ag, and Ti. This is attributed to the high chemical reactivity of borophene as observed from crystal orbital Hamilton population and electron localization function analysis. In an effort to restore the Dirac property, we insert a graphene/hexagonal-boron-nitride (hBN) layer between 8-Pmmn and metal, a technique used in recent experiments for other 2D materials. We show that while the insertion of graphene successfully restores the Dirac nature for all three metals, hBN fails to do so while interfacing with Ti. The quantum chemical insights presented in this work may aid in to access the Dirac properties of 8-Pmmn in experiments.

FIG: (a) Top and side views of 3 × 3 × 1 supercell of 8-Pmmn borophene. The lattice parameters are a = 3.26 Å, b = 4.52 Å, and h = 2.19 Å. The inner and ridge atoms are denoted by blue and green atoms, respectively. (b) Crystal orbital Hamilton population (COHP) analysis and (c) electron localization function (ELF) plot for graphene and 8-Pmmn borophene.

Acknowledgments: The authors acknowledge the Supercomputer Education and Research Center (SERC), Indian Institute of Science (IISc), Bangalore, for CPU- and GPU-based computations. The computational charges were aided by the Mathematical Research Impact Centric Support (MATRICS) scheme of Science and Engineering Research Board (SERB), Government of India, under Grant No. MTR/2019/000047.

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

Cutting-Edge IC Design Workshop

U.S. - Japan Collaboration Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM  (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST) 

Online

The semiconductor industry is facing a number of challenges in building a stable supply chain. The importance of semiconductors was reaffirmed at the global level, and various initiatives were announced to revitalize and support the semiconductor industry, including investment in infrastructure development and human resource development for cutting-edge foundries. Against this backdrop, it is hoped that the creation of next-generation semiconductor technology and the further expansion of the industry will be achieved based on strong cooperation between Japan and the United States. As a phase 1 toward this goal, this workshop will discuss cutting-edge IC design technologies such as open source IC design, ecosystem construction, and human resource development. This workshop was supported by the U.S. Consulate in Fukuoka.

Application deadline is December 12. Please apply individually for DAY-1 and DAY-1the following form (you can also apply for only one of them).

• DAY-1 Application (Click here)
• DAY-2 Application (Click here)

[Participation fee] Free

[Notice] Simultaneous interpretation is available in English and at ZOOM Webinar.

DAY-1: Dec. 5th, 8:00-11:35 AM (JST)

8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

8:05 - 8:10 Welcome Remarks from the U.S. Consulate in Fukuoka

8:10 - 8:40 TBD, Steve Kosier, Skywater

8:40 - 9:10 The Emerging Ecosystem of Open-Source IC Design: IEEE SSCS Activities and Future Goals, Boris Murmann, Chair of the SSCS TC OSE, University of Hawaii

9:10 - 9:40 Human resource development for Semiconductor Technologies in Fukuoka, Koji Inoue, Fukuoka Semiconductor Reskilling Center/Kyushu University, Hideharu Kanaya, Kyushu University,

9:40 - 9:50 Break

9:50 - 10:20 Lab to Fab in the Cloud: Semiconductor Innovation at Amazon, David Pellerin, AWS 

10:20 - 10:50 TBD, Kai Yick, Google Research ML

10:50 - 11:20 Analog and Mixed-Signal IC Design Automation, David Wentzloff, University of Michigan

11:20 - 11:30 Q&A + Panel Discussion

11:30 - 11:35 Conclusion, Mehdi Saligane, University of Michigan

DAY-2: Dec. 6th, 8:00-11:30 AM (JST)

8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

8:05 - 8:35 Innovation by Collaboration: CHIPS Alliance, Rob Mains, CHIPS Alliance, Linux Foundation 

8:35 - 9:05 Developing CMOS+X Platforms for Artificial Intelligence and Beyond, Brian Hoskins, NIST 

9:05 - 9:35 Agile-X: Agile Chip Design and Fabrication Platform, Makoto Ikeda, University of Tokyo

9:35 - 9:45 Break

9:45 - 10:15 The future of semiconductor : chips and chiplets, Dan J. Dechene, IBM Research

10:15 - 10:45 AI Chip Design Center – open hub for chip innovation -, Kunio Uchiyama, National Institute of Advanced Industrial Science and Technology  

10:45 - 11:15 Democratizing EDA Tooling and Chip Design, Johan Euphrosine, Google (Tentative)

11:15 - 11:25 Q&A + Panel Discussion

11:25 - 11:30 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

[お問い合わせ] ic-design-ws 'at' slrc.kyushu-u.ac.jp　（ 'at' を @ で置き換えてください）

GoIT project at Open Source Experience Event

Laboratoire d'Informatique de Paris 6 (LIP6) Sorbonne and CNRS will attend Open Source Experience event on 6-7 December in Paris to present GoIT project

Come and join the European open source community meeting!!

[ read more... ]

Free Silicon Foundation Roadmap

The Free Silicon Foundation (F-Si) has prepared a list of recommendations and a roadmap for the European Commission for the development of open-source silicon in the EU. 

The full text is available to download here 

Executive summary 

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Chapter 1: Table of Contents

After a brief introduction (Chapter 2) which defines the necessary terminology and introduces the political background (Chapter 3), in Chapter 4 we argue that open-source Electronic Design Automation (EDA) tools and open-source silicon are essential instruments to achieve many of the goals set by the Chips Act. This chapter does not provide any recommendations yet.

Chapter 5 we analyse the “Design Platform” foreseen by the Chips Act in the light of the feedback obtained by interrogating multiple European SMEs involved in chip design. Potential problems were identified with the foreseen cloud-based infrastructures. These are related with security, privacy, the too large spectrum of tools, forced upgrades, increased control by EDA vendors, and increased risk of discovery of patent infringement. To mitigate these problems we recommend to support, besides cloud installations, also local EDA installations, and we recommend to support open-source EDA flows besides the commercial flows.

Chapter 6 we analyse the role of standards and standards-setting bodies in the context of open-source. In particular, we highlight how open-source development has needs which are substantially different from the mainstream industrial approach to standardization. We highlight in particular a set of necessary conditions that, in our experience, standards must fulfil in order to be adopted by the open-source community.

Chapter 7 we discuss academia. We argue that academia can and should play a significant role in the development of open-source EDA tools and open-source silicon. For fostering open-source development in universities, we recommend that the metrics to evaluate academics should include open-source projects aside to publications, citations, etc. Next, we highlight how there are two classes of academics, which are both essential: developers of EDA tools and users of EDA tools. Given the near complete disappearance of the former, we recommend that a new generation of professors is hired to develop open-source EDA tools and to revive the corresponding knowledge in Europe. In this Chapter we finally highlight how people who have not been exposed to open-source solutions often don’t appreciate its potential therefore creating a cultural bias. In conclusion, also because of other conflicts of interest, we recommend introducing new and independent personnel in academia.

Chapter 8 we present an open letter about ecological sustainability. The signatories of this letter recommend: 

1. more sober technology, 

2. the “6Rs” (Refurbish, Reuse, Repair, Reliability, Reduce, Recycle) for electronic devices, 

3. external and independent auditors for Life Cycle Assessments (LCAs), 

4. encouraging world-wide regulations to limit the environmental impact in the ICT sector.

Chapter 9 we discuss patent threats and possible upcoming problems for open-source development. Unfortunately, we have no consolidated recommendations yet.

Chapter 10 we briefly discuss possible implications of Artificial Intelligence on chip design. We warn that the advent of AI might produce an increased silicon-technology gap between owners of AI and the others. We recommend putting in place mechanisms to prevent a further power unbalance between large and small actors. A possible mechanism consists of guaranteeing a fully open (i.e. down to silicon) development of AI. 

Chapter 11 we discuss the Cyber Resilience Act (CRA) and we recommend that: 

1. the concept of open-silicon is added to the CRA, and 

2. open-silicon is recognized as a key ingredient to achieve some of the hardware cybersecurity goals.

Chapter 12 we finally present a roadmap for open-source silicon development. First we make a list of open-silicon chips which can be realised immediately or in the near future and highlight their impact. We then recommend to rapidly finance projects similar (in scope and management) to the DARPA OpenRoad project for open-source EDA development. This is our strongest and most important recommendation. Next, we list all political handles that policy can operate to foster open-silicon development. Finally, we present a recommended timeline for the different activities and we conclude.

Acknowledgements

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This document was prepared with help from many people working in university, small organizations and SMEs. Starting from the end of September 2023, it has been reviewed by about twenty people. We are very grateful to all of them for their inputs and feedback.

Funding and disclaimer 

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This work is funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or of the European Commission. Neither the European Union nor the European Commission can be held responsible for them.

Project name: “Go IT!” ID number: 101070660