[webinar] IEEE SCV-EDS: Investigating quantum speed limits with superconducting qubits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Meenakshi Singh. The title of the lecture is ‘Investigating quantum speed limits with superconducting qubits’

When: Friday, Oct. 20, 2023 – 9am to 10am (PDT)
Where: This is an online event and attendees can participate via Zoom.

Registration or Send an email to hiuyung.wong at ieee.org to get the zoom link indicating if you are IEEE member, IEEE EDS member, IEEE Student member

Abstract: The speed at which quantum entanglement between qubits with short range interactions can be generated is limited by the Lieb-Robinson bound. Introducing longer range interactions relaxes this bound and entanglement can be generated at a faster rate. The speed limit for this has been analytically found only for a two-qubit system under the assumption of negligible single qubit gate time. We seek to demonstrate this speed limit experimentally using two superconducting transmon qubits. Moreover, we aim to measure the increase in this speed limit induced by introducing additional qubits (coupled with the first two). Since the speed up grows with additional entangled qubits, it is expected to increase as the system size increases. This has important implications for large-scale quantum computing.

Speaker Bio: Dr. Singh is an experimental physicist with research focused on quantum thermal effects and quantum computing. She graduated from the Indian Institute of Technology with an M. S. in Physics in 2006 and received a Ph. D. in Physics from the Pennsylvania State University in 2012. Her Ph. D. thesis was focused on quantum transport in nanowires. She went on to work at Sandia National Laboratories on Quantum Computing as a post-doctoral scholar. She is currently an Associate Professor in the Department of Physics at the Colorado School of Mines. At Mines, her research projects include measurements of spin-orbit coupling in novel materials and thermal effects in superconducting hybrids. She recently received the NSF CAREER award to pursue research in phonon interactions with spin qubits in silicon quantum dots.

[IHP Career] Research associate for Open PDK Development

Research associate for Open PDK Development (m/f/d)

Developer for Open Source Process Design Kits for SiGe-BiCMOS technolog

Job-ID: 7064/23 | Department: Technology | Salary: as per tariff TV-L | Working time: 40h/week (part-time work option) | Limitation: initially 2 years with option of extension | Entry Date: as soon as possible

The position:

As a member of the group Research & Prototyping Service you will develop Process Design Kit (PDK) for IHP’s BiCMOS technologies and new future technology modules. Your detailed tasks will include programming (e.g. pcells or run decks for DRC and LVS) for commercial as well as open-source tools for ASIC design environments.

Devices descriptions, user guides and test cases are important aspects of your work, too. Implementation of new devices and investigations into new design tools and flows, this includes adaption of tools, will give this position room interesting development opportunities.

Your profile:

You hold a Master's degree in computer science with strong background in semiconductors, physics or electrical engineering. Knowledge in semiconductor devices and programming are of advantage. Your specialized knowledge preferably covers ASIC design environment like Cadence Virtuoso, Mentor/Siemens/Tanner, KeySight ADS or the open source tools like OpenROAD/OpenLane.

Furthermore, you have skills for programming in scripting languages (e.g. Python, Perl or TCL). You are well organized and always keep the overview even with many parallel projects. Thanks to your skillful communication, you are a binding and reliable contact person for our partners.

You are also a strong team player. We are looking for a team member, who is able to structure his or her own work and to bring a well-organized and systematic way of working into the cooperation with creative minds. You are an ideal match for this position, when you have experimental, analytical and problem-solving skills, very strong communicative skills and the ability to quickly learn how to operate the latest technical equipment including various software. It is necessary that you confidently handle the English language. Knowledge of the German language is welcome.

The consolidating of German language skills is expected and highly encouraged, for example in in-house language courses and intensive courses.

Further Information Online Application Form

[conference] FIRST 2023

Website: http://sme.tju.edu.cn/info/1095/2265.htm

English: https://www.aconf.org/conf_194081.html

Date: 30 Oct 2023 (Mon) to 31 Oct 2023 (Tue)

Main Organizer: Tianjin University

Venue: Online

Theme: Interdisciplinarity: The Fusion of Technologies (Semiconductor, Artificial Intelligence, Internet-of-Things, and Communications)

The inaugural FIRST international conference will be held online on Monday, 30th and Tuesday 31st October 2023. Many world-renowned professors, experts and researchers in communication and semiconductor technologies and other related fields at home and abroad will attend this conference. This international conference aims to discuss the open problems and present new solutions that address the challenges of future communication systems, artificial intelligence, internet-of-things, and chip design. Specifically, the role of semiconductors in future communications will be presented and how can the semiconductor and communication industry emerge stronger after the pandemic will be discussed.

This FIRST international conference will be open to relevant enterprises and experts in the field of semiconductors and integrated circuits, providing a professional multi-disciplinary and multi-field exchange and cooperation platform for enterprises, universities and research institutes in the field of semiconductors and integrated circuits, providing innovative ideas for today's increasingly complex and difficult product development, combining cutting-edge scientific research and product innovation more effectively. At the same time, it lays a solid foundation for more in-depth school-enterprise cooperation.

Registration（注册网址）: 中文站 - https://www.aconf.cn/conf_194081.html

[C4P] IJNM - 7th Sino MOS-AK Workshop

Call for Papers

Special issue on the 7th International Sino MOS-AK Workshop

Submission deadline: Sunday, 31 December 2023

The 7th International Sino MOS-AK Workshop was held on 11-13th August 2023 in Nanjing, China. MOS-AK working group has more than 20 years enabling  compact modeling  R&D exchange. For additional detailed info, please refer to MOS-AK website:
http://www.mos-ak.org/nanjing_2023/.

With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. With this background, the workshop aims to strengthen a network and discussion forum among experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of Analytical Modeling, Compact Modeling, Characterization and Simulation techniques for advanced devices, circuits and technologies. Modeling and validation technique of all solid-state devices, including, Si, III-V, power, nanoscale electronic structures and other related new devices are within the scope of the conference. The theme of MOS-AK is "Bridge of Process Technology and Integrated Circuits & Systems Design".

Topics for this call for papers include but not restricted to:

• Advances in semiconductor technologies and processing (CMOS, SOI, FINFET, III-V, Wide band-gap)
• CM of passive active, sensors, and actuators
• Emerging Devices, photonic devices, CMOS, and SOI-based memory cell
• RF/THz device and Power device modeling
• Power device and Power integration
• Reliability modeling
• AI and machine learning in EDA & modeling application
• Nanoscale CMOS devices and circuits
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open-source TCAD/EDA modeling and simulation
• Technology R&D, DFY, DFT and IC Designs
• Chiplet Modeling and Packaging-related modeling
• Foundry/Fabless Interface Strategies, Open Access PDKs
• DTCO & STCO-related EDA tools/technologies
• Other related topics

Guest Editors:

• Jun Zhang
  Nanjing University of Posts and Telecommunications (CN)
• Yuehang Xu
  University of Electronic Science and Technology of China (CN)
• Wladek Grabinski
  MOS-AK (EU)

Submission Guidelines/Instructions

Authors of papers presented at the conference will be invited to submit an extended paper by 31 December 2023 to a special issue of IJNM. Manuscripts for this special issue should adhere to the requirements for regular papers in IJNM as specified in the journal’s Author Guidelines. The manuscripts will be submitted via the IJNM manuscript submission site, https://wiley.atyponrex.com/journal/jnm. Authors must choose the special issue title from the dropdown list on the “Additional Information” tab.

SUBMIT NOW

[book chapters] Equation-Based Compact Modeling

 

Debnath, P., Sarkar, B., & Chanda, M. (Eds.). (2023).

Differential Equation Based Solutions 

for Emerging Real-Time Problems

(1st ed.). CRC Press 

DOI 10.1201/9781003227847

Chapter: Differential Equation-Based Compact 2-D Modeling of Asymmetric Gate Oxide Heterojunction Tunnel FET; By: Sudipta Ghosh, Arghyadeep Sarkar

Abstract: Tunnel Field Effect Transistor (TFET) has emerged as an effective alternative device to replace MOSFET for a few decades. The major drawbacks of MOSFET devices are the short-channel effects, due to which the leakage current increases with a decrease in device dimension. So, scaling down TFET is more efficacious than that of MOSFETs. Sub-threshold swing (SS) is another advantageous characteristic of TFET devices for high-speed digital applications. In TFETs the SS could be well below 60 mV/decade, which is the thermal limit for MOSFET devices and therefore makes it more suitable than MOSFET for faster switching applications. It is observed from the literature studies that the performances of the TFET devices have been explored thoroughly by using 2-D TCAD simulation but an analytical model is always essential to understand the physical behavior of the device and the physics behind this; which facilitates further, the analysis of the device performances at circuit level as and when implemented.

Chapter: Differential Equation-Based Analytical Modeling of the Characteristics Parameters of the Junctionless MOSFET-Based Label-Free Biosensors; by: Manash Chanda, Papiya Debnath, Avtar Singh

Abstract: Recently Field Effect transistor (FET)-based biosensing applications have gained significant attention due to the demand for quick and accurate diagnosis of different enzymes, proteins, DNA, viruses, etc; cost-effective fabrication process; portability and better sensitivity and selectivity compared to the existing biosensors. FET is basically a three-terminal device with source, drain, and gate terminals. Basically, the gate terminal controls the current flow between the source and drain terminals. In FETs, first, a nanogap is created in the oxide layer or in the gate by etching adequate materials. When the biomolecules are trapped inside the nanocavity then the surface potentials change and also the threshold voltage varies. As a result, the output current also changes. Finally, by measuring the changes in the threshold voltage or the device current, one can easily detect the biomolecules easily.