Showing posts with label Sino MOS-AK. Show all posts
Showing posts with label Sino MOS-AK. Show all posts

Oct 9, 2023

[C4P] IJNM - 7th Sino MOS-AK Workshop

Call for Papers
Special issue on the 7th International Sino MOS-AK Workshop


Submission deadline: Sunday, 31 December 2023

The 7th International Sino MOS-AK Workshop was held on 11-13th August 2023 in Nanjing, China. MOS-AK working group has more than 20 years enabling  compact modeling  R&D exchange. For additional detailed info, please refer to MOS-AK website:
http://www.mos-ak.org/nanjing_2023/.

With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. With this background, the workshop aims to strengthen a network and discussion forum among experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of Analytical Modeling, Compact Modeling, Characterization and Simulation techniques for advanced devices, circuits and technologies. Modeling and validation technique of all solid-state devices, including, Si, III-V, power, nanoscale electronic structures and other related new devices are within the scope of the conference. The theme of MOS-AK is "Bridge of Process Technology and Integrated Circuits & Systems Design".

Topics for this call for papers include but not restricted to:

  • Advances in semiconductor technologies and processing (CMOS, SOI, FINFET, III-V, Wide band-gap)
  • CM of passive active, sensors, and actuators
  • Emerging Devices, photonic devices, CMOS, and SOI-based memory cell
  • RF/THz device and Power device modeling
  • Power device and Power integration
  • Reliability modeling
  • AI and machine learning in EDA & modeling application
  • Nanoscale CMOS devices and circuits
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open-source TCAD/EDA modeling and simulation
  • Technology R&D, DFY, DFT and IC Designs
  • Chiplet Modeling and Packaging-related modeling
  • Foundry/Fabless Interface Strategies, Open Access PDKs
  • DTCO & STCO-related EDA tools/technologies
  • Other related topics

Guest Editors:

  • Jun Zhang
    Nanjing University of Posts and Telecommunications (CN)
  • Yuehang Xu
    University of Electronic Science and Technology of China (CN)
  • Wladek Grabinski
    MOS-AK (EU)

Submission Guidelines/Instructions

Authors of papers presented at the conference will be invited to submit an extended paper by 31 December 2023 to a special issue of IJNM. Manuscripts for this special issue should adhere to the requirements for regular papers in IJNM as specified in the journal’s Author Guidelines. The manuscripts will be submitted via the IJNM manuscript submission site, https://wiley.atyponrex.com/journal/jnm. Authors must choose the special issue title from the dropdown list on the “Additional Information” tab.

SUBMIT NOW