[Workshop] QIP

Silicon Quantum Information Processing (QIP) Workshop

Glasgow Marriott Hotel

Wednesday, Sept. 20, 2023

Silicon Quantum Information Processing (QIP) is highly appealing due to excellent spin qubit performances and the expertise of the integrated circuit industry in device scaling. Demonstrations of long-lived, high-fidelity silicon qubits, multi-qubit gates and spin–photon coupling, are promising for the control and interconnect of QIP architectures. Recently, spin qubits in related semiconductors (e.g. germanium) have also emerged as promising implementations of scalable quantum hardware. The formidable challenge of scaling these systems to the level required for meaningful computational applications has also brought to the fore the need for robust cryo-CMOS electronics, which will enable fast control and data processing, as well as schemes to correct errors and protect against decoherence. This meeting will bring together leading researchers from the QIP communities of silicon and related semiconductors, as well as cryo-CMOS designers and engineers who are working at different layers of the “quantum stack”.

10:00AM- 10:10AM	Introduction
10:10AM- 10:40AM	Pablo Cova Farina Quantum dot ladders for quantum computation and simulation
10:40AM-11:00AM	Federico Fedele Automatic techniques for fast and automatic all-rf tuning of quantum devices
11:00AM-11:30AM	Mark Johnson Rapid characterisation of over 1000 silicon quantum dots
11:30AM-11:50AM	Break and refreshments
11:50AM-12:20PM	Gian Salis How are hole-spin qubits in Ge/SiGe heterostructures driven and why do they decohere?
12:20PM-12:40PM	Ross Leon Exchange control in a MOS double quantum dot made on a 300mm process
12:40PM-1:10PM	Asen Asenov A Methodology for Cryogenic PDK Re-Centering Using Experimental Data and TCAD Simulations
1:10PM-2:30PM	Lunch
2:30PM-3:00PM	Masoud Babaie A Cryo-CMOS Receiver for Spin Qubit Gate-Based Readout: from Modelling to Implementation and Verification
3:00PM-3:20PM	Mathieu de Krujif Measurement of classical electronics heating a local quantum dot thermometer in silicon
3:20PM-3:40PM	Janne Lehtinen Custom CMOS platform for quantum processor units
3:40PM-4:00PM	Stavroula Kapoulea Towards the Development of Quantum Computing System-On-Chip: Bringing Electronics Closer to Qubits
4:00PM-4:10PM	Concluding remarks
4:10PM-5:00PM	Refreshments
5:00PM-6:00PM	Lab tour
7:00PM-9:00PM	Conference Dinner

[book] Advanced Ultra Low-Power Semiconductor Devices

Advanced Ultra Low-Power Semiconductor Devices

Design and Applications

Edited by Shubham Tayal, Abhishek Kumar Upadhyay, Shiromani Balmukund Rahi, and Young Suh Song

ISBN: 9781394166411 | (C)2023  Hardcover | 306 pages

Description

This outstanding new volume offers a comprehensive overview of cutting-edge semiconductor components tailored for ultra-low power applications. These components, pivotal to the foundation of electronic devices, play a central role in shaping the landscape of electronics. With a focus on emerging low-power electronic devices and their application across domains like wireless communication, biosensing, and circuits, this book presents an invaluable resource for understanding this dynamic field.

Bringing together experts and researchers from various facets of the VLSI domain, the book addresses the challenges posed by advanced low-power devices. This collaborative effort aims to propel engineering innovations and refine the practical implementation of these technologies. Specific chapters delve into intricate topics such as Tunnel FET, negative capacitance FET device circuits, and advanced FETs tailored for diverse circuit applications.

Beyond device-centric discussions, the book delves into the design intricacies of low-power memory systems, the fascinating realm of neuromorphic computing, and the pivotal issue of thermal reliability. Authors provide a robust foundation in device physics and circuitry while also exploring novel materials and architectures like transistors built on pioneering channel/dielectric materials. This exploration is driven by the need to achieve both minimal power consumption and ultra-fast switching speeds, meeting the relentless demands of the semiconductor industry. The books scope encompasses concepts like MOSFET, FinFET, GAA MOSFET, the 5-nm and 7-nm technology nodes, NCFET, ferroelectric materials, subthreshold swing, high-k materials, as well as advanced and emerging materials pivotal for the semiconductor industrys future.

[conference] 10th Micro Nano 2023

10th International Conference "Micro Nano 2023"

Location: Demokritos Congress Center

Dates: November 2nd-5th 2023

The Micro Nano 2023 Organizing Committee is looking forward to welcoming you to Athens to the 10th International Conference on Micro-Nanoelectronics, Micro-Nanosciences and Nanotechnologies (https://2023.micro-nano.gr), our annual event that brings together Academia, Research and Industry to discuss the latest advancements of the field.

We are happy to announce that the abstract submission is already open and would like to prompt you to submit your work by September 18th. Also, take advantage of the early bird registration discounts, which are open until October the 9th

Visit https://2023.micro-nano.gr/call-for-paper/ to submit your abstract 

and https://2023.micro-nano.gr/fees-registration/ for registration details.

We would like to remind you that this year’s conference includes a Celebratory Special Event for the conference’s 10th Anniversary, scheduled as an Opening Ceremony on the first day (November 2nd, 2023) to commemorate and celebrate 40 years of Microelectronics in Greece. We are also excited about this year’s 

plenary speakers: https://2023.micro-nano.gr/plenary-speakers/

and invited https://2023.micro-nano.gr/invited-speakers/

Check our website for more information on the stimulating presentations that lie ahead.

Dates to remember:

• Abstract submission deadline: September 18th, 2023
• Early-bird registration: October 9th, 2023
• Late poster presentation: October 23rd, 2023

Venue:

• Special Event: Main Hall of the National and Kapodistrian University of Athens (Panepistimiou 30)
• Special Event (Nov.2): “40 years of Microelectronics in Greece”
  https://2023.micro-nano.gr/special-event/

Technical Program: 

• Demokritos Congress Center, NCSR “Demokritos”
  https://2023.micro-nano.gr/final-program/

We are looking forward to seeing you all in November!

On behalf of the Organizing Committee,

Prof. Margarita Chatzichristidi, Conference Chair

Dr. Eleni Makarona, Conference Co-chair

Conference e-mail address: MicroNano2023@chem.uoa.gr

 

[paper] VNWFET-based technology

VNWFET-based technology: from device modelling to standard cell library

Sara Mannaa, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour, 

Ian O’Connor, Alberto Bosio

2023 IEEE 23rd International Conference on Nanotechnology (NANO),

Jeju City, S.Korea, 2023, pp. 576-581

DOI: 10.1109/NANO58406.2023.10231288

Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully, France

Abstract: Vertical Nanowire Field Effect Transistors (VNWFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect capacitance, thereby achieving improved energy-efficiency and being naturally compatible with advanced 3D integration approaches. However, while initial estimations have focused on projections and estimations, no work has so far used a detailed compact model to attempt accurate transistor-level simulations for standard cell library characterization, thus enabling logic synthesis. In this paper, we propose a design flow to make the link from an existing (laboratory-scale) VNWFET technology and the associated compact model, to standard static logic cell design and characterization, and ultimately logic synthesis. To the best of our knowledge, this is the first work to prove the possibility of such a realistic design flow tailored to VNWFET technologies.

Fig: Through actual VNWFET fabrication setting up a design-technology co-optimization (DTCO) approach, the FVLLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to fine-grain hardware / software co-optimisation.

Acknowledgment: This work has been founded by FVLLMONTI European Union’s Horizon 2020 research and innovation programme under grant agreement No 101016776.

Call for Book Chapters

Nanoscale Electronic Device Applications of Carbon Nanotubes,

Graphene, Silicene and Molybdenum Disulfide