#NIST and #Google to Create New Supply of #Chips for Researchers and Startups

#NIST and #Google to Create New Supply of #Chips for Researchers and #Semi Tech Startups https://t.co/hP6Ek2bmVK https://t.co/pdrUROnzzF

— Wladek Grabinski (@wladek60) Jan 19, 2023

---

from Twitter https://twitter.com/wladek60

January 19, 2023 at 01:35PM
via IFTTT

IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 

on Micro/Nanoelectronics, Devices, Circuits and Systems, 

29-31 Jan 2023 (Hybrid Mode)

DATES	LOCATION	HOST	REGISTER
Date: 29 Jan 2023 Time:10:00AM to 06:00PM  (UTC+05:30)  Add Event to Calendar  iCal  Google Calendar	National Institute of Technology Silchar Dept of ECE, NIT Silchar Silchar, Assam India 788010 Building: ECE/CSE Building	National Inst of Technology - Silchar, ED15 Kolkata Section Chapter NANO42 Co-sponsored by Dr. Trupti R. Lenka	Starts Dec.1, 2022 Ends Jan.28,2023 No Admission Charge Register NOW

Agenda with following contribution Distinguished Lecturers: 

• Anil Kottantharayil (anilkg@ieee.org)
• Gananath Dash (gndash@ieee.org)
• Ajit Kumar Panda (akpanda62@hotmail.com)
• Manoj Saxena (msaxena@ieee.org)
• Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
• Samar Saha (samar@ieee.org)
• Hiroshi Iwai (h.iwai@ieee.org)
• Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
• Pei-Wen Li (pwli@nycu.edu.tw)
• Zhou Xing (EXZHOU@ntu.edu.sg)
• Albert Chin (albert_achin@hotmail.com)
• Mansun Chan (mchan@ust.hk)
• Chao-Sung LAI (cslai@mail.cgu.edu.tw)
• Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Register NOW

Neural networks and machine learning approach for compact modeling

[NN] Wang, Qiuwei, Mao Ye, Yao Li, Xiaoxiao Zheng, Jiaji He, Jun Du, and Yiqiang Zhao. "MOSFET modeling of 0.18 μm CMOS technology at 4.2 K using BP neural network." Microelectronics Journal (2023): 105678. DOI: 10.1016/j.sse.2022.108580

Highlights

• The cryogenic characterization of SMIC CMOS technology at 4.2K is presented.
• An optimization model VCCS is proposed to calibrate the cryogenic characteristics.
• BP neural network is, for the first time, used in MOSFET modeling.
• The cryo-model can be applied to SPICE simulator and assist in cryo-CMOS circuit design and simulation.

Fig: The structure of graph-based compact model of FinFET. The model receives the input features such as voltages, geometries, etc. as a vector and predicts the drain current (Ids) and its derivatives as output features.

[ML] Gaidhane, Amol D., Ziyao Yang, and Yu Cao. "Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach." Solid-State Electronics (2023): 108580.

Highlights

• Developed a Graph-based compact model for FinFET.
• Model implemented in Verilog-A for SPICE simulation.
• Requires less number of model parameters and is computationally efficient than BSIM

[mos-ak] [Prennouncement] 7th Sino MOS-AK Workshop in Nanjing (CN)

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

scheduled for August 11-13, 2023 (online/onsite)

Preannouncement and Call for Papers

Together with local host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 7th Sino MOS-AK Workshop in Nanjing (CN) which will be organized as the online/onsite event on August 11-13, 2023 providing an opportunity to meet the internation modeling experts, engineers and researchers. A training course related to SiC topic (device modeling, packaging models, circuits, modules and final application) is planned for the first MOS-AK day, following by two days of the MOS-AK compact/SPICE modeling and its Verilog-A discussions. 

Upcoming, subsequent 7th Sino MOS-AK Workshop in Nanjing (CN) aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors, in particular using Free open source PDKs.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies (eg: using Free open source PDKs)

Important Dates:

• Call for Papers - Jan 2023
• 2nd Announcement - April 2023
• Final Workshop Program - July 2023
• 7th Sino MOS-AK Workshop -  Aug. 11-13, 2023 (online/onsite)

[C4P] IEEE AUTOTESTCON 2023

Deadline to submit abstracts is 15 February 2023

View this email in your browser Call For Papers AUTOTESTCON is the world's premier conference that brings together the military/aerospace automatic test industry and government/military acquirers and users to share new technologies, discuss innovative applications, and exhibit products and services. It is sponsored annually by the Institute of Electrical and Electronic Engineers (IEEE).   AUTOTESTCON will be held at the Gaylord National Harbor Resort, National Harbor, MD, USA, on August 28-31, 2023. The technical program for AUTOTESTCON 2023 will be determined by the interests of those participants submitting for publication, presenting a technical paper, or organizing a technical session. Papers and sessions should cover appropriate topics dealing with increasing DoD systems availability and automatic test technology in particular. Learn More Key Topics » Spiral Development and Evolutionary Acquisition » Flexible Sustainment » Interoperability » Design-For-Test/Built-In-Test » Fault Tolerant Systems » Legacy ATE Challenges » Future Logistics Support Concepts » Contractor Logistics Support » Maintenance Repair & Overhaul » Multinational Integrated Support » Commercialization of Military Maintenance » Electronic Warfare Test and Applications » CMMI Application to ATE/TPS Development » DMSMS Approaches » Organizational, Intermediate, Depot Level Maintenance For The Future » Next Generation Test Systems » Test Program Set Development » Prognostics » Test Requirements Definition and Verification » Factory and Development Test » Software Testing and Research » Development in Instrumentation and Measurement Download CFP Submission Information Abstracts are to be submitted to EDAS no later than February 15, 2023. Submit Paper(s) Here Questions? Website Email Sponsors Copyright © 2023 IEEE, All rights reserved. You are receiving this email because of your membership in IEEE Aerospace & Electronics Systems Society. Our mailing address is: IEEE 445 Hoes Lane Piscataway, NJ 08854-4141 USA IEEE Private Policy Want to change how you receive these emails? You can update your preferences or unsubscribe from this list.