#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers [ST News https://t.co/BTdQoaGlnA] #semi https://t.co/cgX8Jxqtsy
— Wladek Grabinski (@wladek60) Jul 27, 2021
from Twitter https://twitter.com/wladek60
July 27, 2021 at 05:53PM
via IFTTT
Jul 27, 2021
#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers
from Twitter https://twitter.com/wladek60
July 27, 2021 at 05:53PM
via IFTTT
[paper] Above Vth Model for SC DG MOSFETs
David Chuyang Hong; Yuan Taur
An Above Threshold Model for Short-Channel DG MOSFETs
in IEEE TED, vol. 68, no. 8, pp. 3734-3739, Aug. 2021
DOI: 10.1109/TED.2021.3092310.
*Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA
Abstract: An above-threshold I–V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source–drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the Ids-Vds and Ids-Vgs characteristics generated by the model are shown to be consistent with TCAD simulations.
Figure below shows the schematic of a DG MOSFET (undoped). The device operation is governed by 2-D Poisson’s equation
Fig: Schematic of a DG MOSFET. The parameters assumed are tsi=4nm, ti=2nm, εsi=εi=11.8ε0, with channel length L ranging from 15 to 7nm. The gate work function is 0.28eV below that of intrinsic silicon so Vt=0.247V.
Jul 26, 2021
[paper] VNWFET Including Tied Compact Model
Arnaud Poittevin1, Chhandak Mukherjee2, Ian O’Connor1, Cristell Maneux2, Guilhem Larrieu3,4, Marina Deng2, Sebastien Le Beux1, Francois Marc2, Aurélie Lecestre3, Cedric Marchand1,
and Abhishek Kumar3
3D Logic Cells Design and Results Based on Vertical NWFET Technology
Including Tied Compact Model
In: Calimera A. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. pp 301-321 Springer, Cham.
DOI: 10.1007/978-3-030-81641-4_14
2 University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France
3 Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse, France
4 Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo, Japan
Abstract. Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50 nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and to carry out a performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7 nm FinFET-based inverters.
Fig: Perspective view of the Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET)
Acknowledgments: This work was supported by the French RENATECH network (French national nanofabrication platform) and by the LEGO project through ANR funding (Grant ANR-18-CE24-0005-01).
[paper] NCFET CMOS Logic
Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE,
Timothy Philip, Member, IEEE
Junction Design and Complementary Capacitance Matching
for NCFET CMOS Logic
IEEE J-EDS 2021
DOI 10.1109/JEDS.2021.3095923
IBM Research, Albany, NY 12203
* IBM T.J. Watson Research Center, Yorktown Heights,
NY 10598
Abstract: Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ ferroelectric/ metal/ insulator/ semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DC optimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.
Fig: Equivalent capacitance network and illustrative C-V curve showing NMOS and NC curves. CNC > CINV results in non-hysteretic switching, but low voltage gain in the off-state due to CNC >> COV. Setting CNC to CNC2, which is matched more closely to COV, results in very low SS, but also hysteretic switching as CNC2 < CINV.
Acknowledgment: The authors would like to thank Paul Solomon and Prof. Sayeef Salahuddin for insightful discussions, as well as Synopsys for technical support.
Jul 21, 2021
[Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
18th MOS-AK ESSDERC/ESSCIRC Workshop
Grenoble, Sept. 6, 2021
Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.
The MOS-AK Workshop Program is available online:
Venue: Online MOS-AK Webinar;
use the online form/link below to register.
Online Registration is open
any related enquiries can be sent to registration@mos-ak.org
Post-workshop publications, selected, the best papers will be recommended for further publication in the special compact/SPICE modeling issue of the Solid State Electronics.
-- W.Grabinski; MOS-AK (EU)
WG210721
Subscribe to:
Comments (Atom)