Apr 7, 2021

[papers] compact modeling

Rabnawaz Sarmad Uqaili, Faraz Bashir Soomro, Junaid Ahmed Uqaili, Ahsin Murtaza Bughio 
and Khalid Ali Khan
Study on Compact Equivalent Circuit Model for RF CMOS Transistor 
International Journal of Scientific & Technology Research 
Vol.10, Issue 02, February 2021 ISSN 2277-8616

Abstract: In this study, a physical-based radio-frequency (RF) compact equivalent circuit model (CECM) for complementary metal-oxidesemiconductor (CMOS) transistor and its parameter extraction is presented. The whole structure of CECM that includes a small-signal equivalent circuit model of the transistor, a MOSFET small-signal substrate model, an input and output ground-signal-ground (GSG) pad model, a pad coupling model and a metal interconnection model are briefly studied and discussed. Based on this study, a complete test structure model for RF CMOS is designed and the initial values of parameters are extracted by using the analytical method. The multi-bias scattering parameters (S-Parameters) of model correspondence to the experimentation are validated up to 66 GHz and 220 GHz respectively. A good agreement has been achieved between the simulation and experimental under multi-bias conditions.
Fig: Complete CECM for RF CMOS transistor with an entire test structure.


El Mashade, Mohamed B., and Ahmed Abdel Monem
Transient model for modern microelectronic devices applicable to EKV PMOS model 
Radioelectronics and Communications Systems 
Vol.64, no. 2 (2021): 64-79

Abstract: Massive advances in microelectronic manufacturing technology with an exponential growth of their complexity and speed are needed to ensure a continuous development of novel techniques, structures, devices, circuits and systems. This paper is intended for the introduction of a new PMOS transient model for modern microelectronic devices that provides a fast transient response. Such suggested model expresses the transient terminal currents as polynomial functions of the normalized channel charge densities at the channel bounds with the assistance of a modified version of the cubic spline collocation methodology in symmetrical telescopic fashion. Additionally, the optimum number of segments, which is suitable for the new version of the cubic spline collocation algorithm, is investigated. Moreover, the normalized channel charge density at collocation points is modeled in terms of its values at the channel bounds through the quasi-static approach. Furthermore, by means of introducing an inverse function for the normalized overdrive channel voltage, the transient terminal currents are formulated as a function of the terminal voltages. In comparison with usual cubic spline collocation structure, the novel model has much better accuracy in its application to EKV structure. The developed model has been applied to the standard 0.15 mm technology and validated by MATLAB R2014a. The obtained results demonstrate that it gives a very high degree of relative accuracy, on average of 99%, for the total time and exhibits absolute error of less than 5% of the maximum value, in its worst case.


Rakeshkumar Mahto and Reshma John 
Modeling of Photovoltaic Module 
(April 1st 2021)
DOI: 10.5772/intechopen.97082. 

Abstract: A Photovoltaic (PV) cell is a device that converts sunlight or incident light into direct current (DC) based electricity. Among other forms of renewable energy, PV-based power sources are considered a cleaner form of energy generation. Due to lower prices and increased efficiency, they have become much more popular than any other renewable energy source. In a PV module, PV cells are connected in a series and parallel configuration, depending on the voltage and current rating, respectively. Hence, PV modules tend to have a fixed topology. However, in the case of partial shading, mismatching or failure of a single PV cell can lead to many anomalies in a PV module’s functioning. If proper attention is not given, it can lead to the forward biasing of healthy PV cells in the module, causing them to consume the electricity instead of producing it, hence reducing the PV module’s overall efficiency. Hence, to further the PV module research, it is essential to have an approximate way to model them. Doing so allows for understanding the design’s pros and cons before deploying the PV module-based power system in the field. In the last decade, many mathematical models for PV cell simulation and modeling techniques have been proposed. The most popular among all the techniques are diode based PV modeling. In this book chapter, the author will present a double diode based PV cell modeling. Later, the PV module modeling will be presented using these techniques that incorporate mismatch, partial shading, and open/short fault. The partial shading and mismatch are reduced by incorporating a bypass diode along with a group of four PV cells. The mathematical model for showing the effectiveness of bypass diode with PV cells in reducing partial shading effect will also be presented. Additionally, in recent times besides fixed topology of series–parallel, Total Cross-Tied (TCT), Bridge Link (BL), and Honey-Comb (H-C) have shown a better capability in dealing with partial shading and mismatch. The book chapter will also cover PV module modeling using TCT, BL, and H-C in detail.

Available: https://www.intechopen.com/online-first/modeling-of-photovoltaic-module


#Intel to try to become a #foundry, AGAIN?

 



from Twitter https://twitter.com/wladek60

April 07, 2021 at 02:02PM
via IFTTT

[paper] Compact Modeling as a Bridge between Technologies and ICs


Compact Modeling as a Bridge 
between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits
AB Bhattacharyya and Wladek Grabinski
IETE Journal of Research 58(3):179-180 (May 2012)
DOI: 10.4103/0377-2063.97322

Abstract: The quality of the integrated circuits analysis, required in present contemporary design flows, is directly linked to the accuracy of its basic components—the Compact Model/Simulation Program with Integrated Circuit Emphasis (SPICE) Model. The compact/SPICE modeling is an essential research activity bridging scaled semiconductor technologies and advanced designs of the integrated circuits. To enable complete access to the new advanced semiconductor technologies, the designers have to frequently update their Computer-Aided Design (CAD) tools with accurate definition of the semiconductor device models that can be implemented into the CAD circuit simulators. The models must preferably be physics-based to account for complex dependencies of the device properties and defined in standard, high-level language, i.e., Verilog-A, to simplify access and implementation into the CAD tools. For the state of the art advanced CMOS technologies (analog, HV, SOI), both modeling and characterization are challenging tasks that will be emphasized in this special issue of Compact Modeling. (REF) Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits. 

Available from: <http://www.mos-ak.org/india/>
and https://www.researchgate.net/publication/278384752_Compact_Modeling_as_a_Bridge_between_Scaled_Semiconductor_Technologies_and_Advanced_Designs_of_the_Integrated_Circuits

Apr 6, 2021

What China is to #India, #USA is to #China



from Twitter https://twitter.com/wladek60

April 06, 2021 at 03:28PM
via IFTTT

[C4P] DevIC 2021

DevIC 2021: Call for Papers

DevIC 2021 Logo

IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC, technically co-sponsored by IEEE EDS Kolkata Chapter  organizes International conference 4th Int. Conference DevIC 2021 “Devices for Integrated Circuit (DevIC)”.  There will be keynote lectures/talks, tutorials, and oral presentations  by eminent researchers. The conference organizers invite original papers in the research areas of various aspects of semiconductor technology and circuits that creates an opportunity to symbiosis on topic ranging from process technology to system-on-chip. Articles announcing significant and original results are highly requested. Papers are solicited across the general field of electronic devices. Topics of interest include, but are not limited to;
  • CMOS Processes, Devices and Integration;
  • VLSI Technology and Circuits;
  • Innovative Systems;
  • Emerging Non-CMOS Devices & Technologies;
  • Device Modelling & Simulation; 
  • Device Characterization, Reliability & Yield; 
  • Devices with New material systems;
  • Devices for Low power applications;
  • Low dimensional devices;
  • Low dimensional Semiconductors; 
  • Design and Simulation of Circuits with nanoscale devices;
  • MEMS, Sensors & Display Technologies;
  • Advanced & Emerging Memories; 
  • High frequency wireless communication;