Jan 5, 2021

[paper] Analysis of 2D Transistors

Guoli Li, Zizheng Fan, Nicolas André, Member, IEEE, Yongye Xu, Ying Xia, Benjamín Iñíguez, Fellow, IEEE, Lei Liao, Senior Member, IEEE, and Denis Flandre, Senior Member, IEEE
Non-Linear Output-Conductance Function for Robust Analysis of Two-Dimensional Transistors
IEEE Electron Device Letters, 42(1), pp.94-97
DOI: 10.1109/LED.2020.3042212

Abstract: In this work, we explore the outputconductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the currentvoltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

G-Function Model (for Linear and Non-Linear Cases), the Rch and Rc can be calculated for both the Ohmic and Schottky contacts in the 2D transistors: 


Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2018YFA0703700; in part by the National Natural Science Foundation of China under Grant 61925403, Grant 61851403, and Grant 62004065; in part by the Hunan Natural Science Foundation under Grant 2020JJ5087; and in part by the Technology Program (Major Project) of Changsha under Grant kq1902042.


[paper] Aged MOSFET and Its Compact Modeling

F. A. Herrera, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch and H. Takatsuka, Universal Feature of Trap-Density Increase in Aged MOSFET and Its Compact Modeling
SISPAD, Kobe, Japan, 2020, pp. 109-112
DOI: 10.23919/SISPAD49475.2020.9241674

Abstract: Our investigation focuses on accurate circuit aging prediction for bulk MOSFETs. A self-consistent aging modeling is proposed, which considers the trap-density Ntrap increase as the aging origin. This Ntrap is considered in the Poisson equation together with other charges induced within MOSFET. It is demonstrated that a universal relationship of the Ntrap increase as a function of integrated substrate current, caused by device stress, can describe the MOSFET aging in a simple way for any device-operating conditions. An exponential increase with constant and unitary slope of the Ntrap is found to successfully predict the aging phenomena, reaching a saturation for high stress degradation. The model universality is verified additionally for any device size. Comparison with existing conventional aging modeling for circuit simulation is discussed for demonstrating the simplifications due to the developed modeling approach

Fig: Schematic of the density-of-state (DOS) model as a function of the state-energy difference from the conduction-band edge, with two parameters gc and Es introduced as new model features.


Jan 4, 2021

[paper] Compact Modeling of Carbon Nanotube FETs

A Compact and Robust Technique for the Modeling and Parameter Extraction 
of Carbon Nanotube Field Effect Transistors
Laura Falaschetti1, Davide Mencarelli1, Nicola Pelagalli1, Paolo Crippa1, Giorgio Biagetti1,
Claudio Turchetti1,George Deligeorgis2, and Luca Pierantoni1
Electronics 2020, 9(12), 2199; 
DOI: 10.3390/electronics9122199

1 Department of Information Engineering, Marche Polytechnic University, 60131 Ancona, Italy
2 Microelectronics Research Group (MRG/IESL), FORTH, Greece


Abstract: Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.
Figure 2. 3D structure of CNTFET. Reprinted, with permission, from [I and II]

Aknowlwgement: This research was supported by the European Project “NANO components for electronic SMART wireless circuits and systems (NANOSMART)”, H2020—ICT-07-2018-RIA, n. 825430.

References:
[I] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 2007, 54, 3186–3194
[II] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 2007, 54, 3195–3205 




Tentative Technical Program Schedule of the Webinar Series

The Tentative Technical Program Schedule of the Webinar Series 
jointly organized by 
The National Academy of Sciences India - Delhi Chapter 
and Science Foundation & MoE-IIC-DDUC Chapter,
Deen Dayal Upadhyaya College (University of Delhi) 
under the aegis of DBT Star College Program

Kindly see the attachment: for attending one or more Webinars, you are requested to register yourself with the ZOOM Webinar Link https://us02web.zoom.us/webinar/register/WN_iXRnhVc9SxWrSOD9CWTITA and also join the TELEGRAM group (https://t.me/joinchat/UEnJfvW8kcHf_Jmo) for receiving all updates about the Webinar Series. The Exact title of the Talks (which are missing as of now) and the time shall be shared by January 25, 2021 in the telegram group.

Kindly forward this message and attachment to your students and colleagues so that they can also register and join the telegram group.
  • E-Certificate will be provided like earlier programs.
  • Zoom Platform will be used for conducting Online Programs
Coordinator:
Dr. Manoj Saxena | डॉ मनोज  सक्सेना 
Program Coordinator - MoE IIC DDUC Chapter
Associate Professor | सह - आचार्य
Department of Electronics | इलेक्ट्रॉनिक्स विभाग
Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज
University of Delhi | दिल्ली विश्वविद्यालय
Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -, नई दिल्ली -११००७८
India | भारत

What Might the “#1nm #Node” Look Like? by Tom Dillinger; Semiwiki https://t.co/aP6kX33h0W #semi https://t.co/noo3g0hMSZ



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