Nov 2, 2020

[paper] Process Induced Vt Variability

Mandar S. Bhoir, Member, IEEE, Thomas Chiarella, Jerome Mitard, Naoto Horiguchi, Member, IEEE, and Nihar Ranjan Mohapatra, Senior Member, IEEE
Vt Extraction Methodologies Influence Process Induced Vt Variability:
Does This Fact Still Hold for Advanced Technology Nodes? 
IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4691-4695, Nov. 2020
DOI: 10.1109/TED.2020.3025750.

Abstract: In this work, we have investigated the influence of Vt extraction procedure on overall Vt variability of sub-10 nm Wfin FinFETs. Using six different Vt extraction techniques (These are 1) constant current (CC) technique, 2) extrapolation in linear regime [ELR, also known as maximum trans-conductance (gm)] technique, 3) trans-conductance extrapolation (TCE) technique, 4) second-derivative (SD) technique, 5) ratio method (RM); and 6) transition method (TM) [1]) we have experimentally demonstrated that the Vt variability is independent of Vt extraction procedure (unlike reported earlier). Furthermore, through systematic evaluation on commonly used Vt extraction techniques, the physics behind this anomalous behavior is investigated. It is shown that the significant variation in metal gate work-function and gate dielectric charges in advanced CMOS nodes is mainly responsible for this behavior. This claim is further validated for FinFETs with deeply scaled fin-width and effective oxide thickness (EOT).


Fig: (a) Schematic illustration of different process-variability sources in FinFET; 
(b)Transfer characteristics for FinFETs with similar Vt, CC but different RSD.
These FinFETs have different Vt, ELR because of RSD induced gm, max variations

Acknowleegement: This work was supported in part by the Visvesvaraya Ph.D. Scheme, MeitY, Government of India MEITY-PHD-250 and in part by the Horizon 2020 ASCENT EU Project (Access to European Nanoelectronics Network) under Project 654384.

References:
[1] A. Ortiz-Conde, F. G. Sánche, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, “A review of recent MOSFET threshold voltage extraction methods,” Microelectron. Rel., vol. 42, no. 4, pp. 583—596, 2002, doi: 10.1016/S0026-2714(02)00027-6

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Oct 30, 2020

Video Tutorial: What is Verilog-A

Video Tutorial: What is Verilog-A

Verilog-A is a behavioural modelling language for analog circuits from the Verilog Family. It is the subset of Verilog-AMS. Verilog-A HDL is derived from the IEEE 1364 Verilog HDL specification. The intent of Verilog-A HDL is to let designers of analog systems and integrated circuits create and use modules that encapsulate high-level behavioural descriptions as well as structural descriptions of systems and components.

Reference: 
[1] OVI Verilog-A LRM , 1996
[2] https://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/verilogaref.pdf
[3] A New Approach to Compact Semiconductor device Modelling with Qucs Verilog-A analog module synthesis, M.E Brinson & V Kuznetsov, International Journal of Numnerical Mdelling, 2015
[4] https://github.com/cogenda/VA-BSIM48/blob/master/bsim4_release.va

[PhD Thesis] III-V MOS-HEMTs for 100-340GHz Communications Systems

UNIVERSITY OF CALIFORNIA
Santa Barbara
III-V InxGa1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems
A dissertation for PhD degree in Electrical and Computer Engineering
by Brian David Markman

Abstract: This work summarizes the efforts made to extend the current gain cutoff frequency of InP based FET technologies beyond 1THz. Incorporation of a metal-oxide-semiconductor field effect transistor (MOSFET) at the intrinsic Gate Insulator-Channel interface of a standard high electron mobility transistor (HEMT) has enabled increased gm,i by increasing the gate insulator capacitance density for a given gate current leakage density. Reduction of RS,TLM from 110 Ω.μm to 75Ω.μm and Ron(0) from 160Ω.μm to 120Ω.μm was achieved by removing/thinning the wide bandgap modulation doped link regions beneath the highly doped contact layers. Process repeatability was improved by developing a gate metal first process and Dit was improved by inclusion of a post-metal H2 anneal. InxGa1-xAs / InAs composite quantum wells clad with both InP and InxAl1-xAs were developed for high charge density and low sheet resistance to minimize source resistance. 
Figure a) InP-based HEMT b) III-V DC optimized MOSFET c) proposed InP-based MOS-HEMT

[Citation] Markman, B. D. (2020). III-V InxGa1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems. UC Santa Barbara. ProQuest ID: Markman_ucsb_0035D_14853. Merritt ID: ark:/13030/m5v4681j. Retrieved from https://escholarship.org/uc/item/6st812pb