#India now ranks among the #Top10 countries in terms of the number of #opensource projects [https://t.co/5VnCn8CErA] https://t.co/v2IsUB9ZZL https://t.co/ScATobwByx

#India now ranks among the #Top10 countries in terms of the number of #opensource projects [https://t.co/5VnCn8CErA] https://t.co/v2IsUB9ZZL pic.twitter.com/ScATobwByx

— Wladek Grabinski (@wladek60) September 8, 2020

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[paper] RF Small-Signal Model for Four-Port Network MOSFETs

A High-Frequency Small-Signal Model for Four-Port Network MOSFETs

Alejandro Roman-Loera¹, Member, IEEE, Anurag Veerabathini², Member, IEEE, Luis A.Flores-Oropeza¹, Member, IEEE, and Jaime Ramirez-Angulo³, Life Fellow, IEEE

IEEE 63rd IMWSCAS 2020

DOI:10.1109/mwscas48704.2020.9184475 

¹Electronic Systems Department, Universidad Autonoma de Aguascalientes, Mexico.
²Maxim Integrated, Chandler, AZ, USA.
³Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA.

Abstract: A high-frequency small-signal model for a MOSFET is proposed considering the parasitic capacitances associated with each terminal that is critical in the design of high-frequency amplifiers. The proposed model allows in obtaining a closed form expression for poles and zeros due to parasitic elements along with the conventional poles and zeros. This model gives an additional degree of freedom in choosing the location of poles and zeros to improve the frequency response. The proposed high-frequency small-signal model for MOSFET is validated in simulation by implementing a high-frequency voltage follower in 0.18µm CMOS process. The proposed model shows the existence of a zero in a voltage follower that is introduced by the parasitic elements at high-frequencies and it is validated with implementation.

Fig: Small signal equivalent circuit of a 4-port MOSFET (a) Conventional model, (b) Model with substrate parasitics, and (c) Model with additional parasitics, and (d) Proposed model.

Acknowledgment: This work has been supported by PRODEP program from SEP (Secretariat of Public Education, Mexico) and Universidad Autonoma de Aguascalientes, Aguascalientes, Mexico.

#25 #Microchips That Shook the #World - IEEE Spectrum https://t.co/XCdh3S0ClW #semi https://t.co/JFWuLICVDT

#25 #Microchips That Shook the #World - IEEE Spectrum https://t.co/XCdh3S0ClW #semi pic.twitter.com/JFWuLICVDT

1968 Fairchild Semiconductor μA741 Op-Amp
1971 Signetics NE555 Timer
1971 Western Digital WD1402A UART
1973 Mostek MK4096 4-Kilobit DRAM
1975 MOS Technology 6502 Microprocessor
1976 Zilog Z80 Microprocessor
1978 Texas Instruments TMC0281 Speech Synthesizer
1979 Intel 8088 Microprocessor
1979 Motorola MC68000 Microprocessor
1983 Intersil ICL8038 Waveform Generator
1983 Texas Instruments TMS32010 Digital Signal Processor
1985 Acorn Computers ARM1 Processor
1985 Chips & Technologies AT Chip Set
1985 Xilinx XC2064 FPGA
1986 Kodak KAF-1300 Image Sensor
1987 Sun Microsystems SPARC Processor
1987 Texas Instruments Digital Micromirror Device
1988 Computer Cowboys Sh-Boom Processor
1989 Toshiba NAND Flash Memory
1993 Microchip Technology PIC 16C84 Microcontroller
1994 Amati Communications Overture ADSL Chip Set
1997 IBM Deep Blue 2 Chess Chip
1997 Micronas Semiconductor MAS3507 MP3 Decoder
1998 Tripath Technology TA2020 AudioAmplifier
2000 Transmeta Corp. Crusoe

— Wladek Grabinski (@wladek60) September 7, 2020

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[paper] Vertical Graphene–hBCN Heterostructure TFETs

A comparative computational study of tunneling transistors

based on vertical graphene–hBCN heterostructures

Mahsa Ebrahimi¹, Ashkan Horri¹, Majid Sanaeepur², and Mohammad Bagher Tavakoli¹

J. Appl. Phys. 127, 084504 (2020); DOI: 10.1063/1.5130777

Published Online: 28 February 2020

¹Department of Electrical Engineering, Arak Branch, Islamic Azad University, Arak, Iran
²Department of Electrical Engineering, Faculty of Engineering, Arak, Iran

ABSTRACT In this paper, the electrical characteristics of tunneling transistors based on vertical graphene and a hexagonal boron-carbon-nitrogen (hBCN) heterostructure are studied and compared theoretically. We have considered three different types of hBCN, i.e., BC₂N, BC₂N₀, and BC₆N as a tunneling barrier. Our simulation is based on the nonequilibrium Green’s function formalism along with an atomistic tightbinding (TB) model. The TB parameters are obtained by fitting the band structure to first-principles results. By using this method, electrical characteristics of the device, such as the ION=IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. For a fair comparison, the effects of geometrical variations and number of tunneling barrier layers on the electrical parameters of the device are simulated and investigated. We show that, by an appropriate design, the device can be used for low-power or high-performance applications. The device allows current modulation exceeding 106 at room temperature for a 0.6 V bias voltage.

FIG. DFT Band structure for (a) graphene - hBC₂N₀ - graphene (b) graphene - hBC₂N - graphene and (c) graphene - hBC₆N - graphene supercell. BC and BV represent barrier height in the conduction band and valence band, respectively, all simulated with QUANTUM ESPRESSO: A modular and opensource software for quantum simulations of materials

OFETs Compact Modeling

Advances in Compact Modeling of Organic Field-Effect Transistors

Sungyeop Jung¹, Member, IEEE, Yvan Bonnassieux², Gilles Horowitz², Sungjune Jung¹, Member, IEEE, Benjamin Iñiguez³, Fellow, IEEE, and Chang-Hyun Kim⁴, Senior Member, IEEE

IEEE J-EDS (Early Access)

DOI: 10.1109/JEDS.2020.3020312

¹Future IT Innovation Laboratory and Department of Creative IT Engineering, Pohang University of Science and Technology, Pohang 37673, South Korea.
²LPICM, Ecole Polytechinque, CNRS, 91128 Palaiseau, France.

³DEEEA, Universitat Rovira i Virgili, Tarragona 43007, Spain.

⁴Department of Electronic Engineering, Gachon University, Seongnam 13120, South Korea

Abstract: In this review, recent advances in compact modeling of organic field-effect transistors (OFETs) are presented. Despite the inherent strength for printed flexible electronics and the extremely aggressive research conducted over more than three decades, the OFET technology still seems to remain at a relatively low technological readiness level. Among various possible reasons for that, the lack of a standard compact model, which effectively bridges the device- and system-level development, is clearly one of the most critical issues. This paper broadly discusses the essential requirements, up-to-date progresses, and imminent challenges for the OFET compact device modeling toward a universal, physically valid, and applicable description of this fast-developing technology.

Figure (a) Cross-sectional illustration and (b) circuit diagram with multi-component overlap capacitances of the printed 3-D organic complementary inverter, and (c) measured and simulated transient output voltage of an 11-stage ring oscillator.