Aug 26, 2020

[paper] SiC MOSFET Corner and Statistical SPICE Model Generation

SiC MOSFET Corner and Statistical SPICE Model Generation
Canzhong He, James Victory* , Yunpeng Xiao**, Herbert De Vleeschouwer+
Elvis Zheng++, ZhiPing Hu++ 
 ISPSD, September 13-18, 2020, Vienna, Austria
DOI: 10.1109/ISPSD46842.2020.9170091

   Power Design Enablement, ON Semiconductor, Mountain Top, Pennsylvania/USA
 *Power Design Enablement, ON Semiconductor, Aschheim, Germany
**Power Design Enablement, ON Semiconductor, Shanghai, China 
 +Wide Bandgap Technology Development, ON Semiconductor, Oudenaarde, Belgium 
++Product & Test Development Center, ON Semiconductor, Suzhou, China

Abstract: This paper presents a novel approach to generate corner and statistical SPICE models for SiC MOSFETs. The technique is derived from the mature IC industry standard approach known as Backward Propagation of Variance. Physically based, scalable SiC MOSFET SPICE models are required to simulate the correlations between electrical specifications and process variations. The methodologies presented are applicable to other power discrete devices such as super-junction MOSFETs, IGBTs, and GaN HEMTs.

Fig.: SiC MOSFET (a) Cross Section, (b) Subcircuit SPICE Model




Aug 25, 2020

[paper] Native High-k Oxides for 2D Transistors

Yury Yu. Illarionov1,2, Theresia Knobloch1 and Tibor Grasser1
Native high-k oxides for 2D transistors
Nature Electronics vol. 3, pp 442–443 (2020)
Published online: 05 August 2020
DOI: 10.1038/s41928-020-0464-2

1Institute for Microelectronics, TU Wien, Vienna, Austria
2Ioffe Physical-Technical Institute, St Petersburg, Russia

Abstract: The two-dimensional semiconductor Bi2O2Se can be oxidized to create an atomically thin layer of Bi2SeO5 that can be used as the insulator in scaled field-effect transistors.

Fig.: Development of FETs with Bi2O2Se channels and native Bi2SeO5 insulators. a.) Step-by-step oxidation of multilayer Bi2O2Se towards Bi2SeO5 and the crystal structure of the two materials. b.) Cross-sectional scanning transmission electron microscopy image confirming the atomically sharp interface. c.) Schematic of the top-gated devices fabricated with a native gate oxide. d.) Gate transfer characteristics of the devices with a 4.6-nm-thick Bi2SeO5 layer (EOT below 1 nm)

Analog IC Designer's Handbook

by Jean-Francois Debroux
 
Abstract: Analog IC design is one of the particular design activities where designers get feedback on their choices only months after they finish their design and where the cost of even the smallest design change is huge.
This has historically brought the need for new tools such as SPICE, the ancestor of almost all the electric simulators, so as to give feedback on the design choices before actually getting the prototypes. This should also have deeply impacted the design methods, and it has, but the availability of simulators has finally allowed the old “try and fix” method not only to survive but also to stay very popular.
If tools such as electric simulators have gained popularity in most electronic design fields, even out of the IC design world, methods such as the TOP-DOWN approach are not as popular as they should be, especially in the analog design community, even in the analog IC design microcosm. This is probably because this method is felt as difficult to use practically even though most designers agree that it is the right approach.
The goal of this book is to show that the TOP-DOWN approach for analog design is not only valid but that it is one of the most powerful available methods to create good analog design without sacrificing the time to market. This method creates faster and better designs but requires a good understanding of the method itself, of course, but also of the underlying techniques and of the basic design elements.
After a general introduction of the TOP-DOWN method goals and principles in the first part, the second part presents and details analog IC design elements from components to basic building blocks with a strong emphasis on practical aspects. Various additional design techniques are then detailed in the third part. The reader is then ready for the main course, a series of design examples based on the TOP-DOWN method that are grouped in the fourth part. These examples are processed the way they are in real life, from specification to implementation, from general considerations down to implementation details. Analysis of existing circuits is useful for learning but real life design is synthesis, not analysis.
Finally, the fifth part introduces or reminds useful basic concepts and presents the notation in use through the book.
The methods and techniques described in this book have been used by the author through 25 years of analog and mixed signal ICs design experience in various application fields including RF and sensor signal conditioning for various markets such as industrial, automotive and aerospace. The author feels that the method he presents in this book can help many analog electronic designers in their day to day work and hopes it will bring both a deeper understanding of design and a broader view over design activities. [read more...]

Experience: See  Jean-Francois Debroux profile on LinkedIn

Aug 24, 2020

Fwd: Announcement of Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020) jointly organized by Science Foundation and MHRD-IIC-DDUC Chapter, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (Under the aegis of DBT Star College Program)

On behalf of Science Foundation and MHRD-IIC-DDUC Chapter, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (Under the aegis of DBT Star College Program), I would like to invite you to kindly register for the Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates scheduled for September 14-19, 2020.

The workshop is likely to be supported by the Science Academies and will be organized using CISCO WEBEX/Microsoft Teams.

All Interested Science and Engineering Students and Faculty Members are requested to kindly register on 
or before August 25, 2020 via link appended below

There is NO REGISTRATION FEES. I request you to kindly motivate your students and colleagues to register for the same.


Organizing Committee
  • Professor Anurag Sharma, FNA, FNASc, FASc, FNAE, JC Bose National Fellow (SERB), Department of Physics, IIT Delhi (Convener-Workshop)
  • Professor Ajoy Ghatak, NASI Meghnad Saha Distinguished Professor, Chairperson-NASI Delhi Chapter.
  • Dr. Manoj Saxena, Coordinator-Workshop, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (msaxena@ddu.du.ac.in)
  • Committee Members of Science Foundation, MHRD-IIC-DDUC Chapter and DBT Star College Program of  Deen Dayal Upadhyaya College, University of Delhi.
with regards

Dr. Manoj Saxena | डॉ मनोज  सक्सेना 
Associate Professor सह - आचार्य
Department of Electronics | इलेक्ट्रॉनिक्स विभाग
Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज
University of Delhi | दिल्ली विश्वविद्यालय
Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -, नई दिल्ली -११००७८
India | भारत

ResearcherID-Thomson Reuters : http://www.researcherid.com/rid/K-3863-2015 

Please do not print this email unless it is absolutely necessary. Spread environmental awareness. 

Fwd: IEEE-EDS Santa Clara Valley/San Francisco Chapter August Seminar (Webex only)

Please note that this seminar is now WEBEX participation only! 

Memory Errors in Production Systems – Insights from the Field
Speaker: Dr. Sudhanva Gurumurthi, Principal Member of Technical Staff, AMD
Friday, August 28, 2020 at 12PM – 1PM PDT

Abstract: Memory reliability is important for the correct operation of computing systems. While technology scaling has paved the way for improvements in the capacity and energy-efficiency of memory, the reliability aspects of such scaling must be well characterized and addressed in the design of computer hardware. AMD has collected and analyzed memory reliability data from several production systems running in data centers. This data spans several generations of DRAM technologies, as well as SRAM. This talk will first explain how bit-cell reliability can impact on the design and use of computing hardware and highlight the importance of studying memory faults from commercial hardware in the field. The talk will then present memory reliability data and insights from AMD's field studies and discuss their implications from the viewpoint architecting resilient systems.

Speaker Bio: Sudhanva Gurumurthi is a Principal Member of the Technical Staff at AMD, where he leads advanced development in Reliability, Availability, and Serviceability (RAS). He used to be an Associate Professor with tenure in the Computer Science Department at the University of Virginia. Sudhanva is a recipient of the NSF CAREER Award, a Google Focused Research Award, two Google Faculty Research Awards, and other NSF and industry awards. He is a Senior Member of the IEEE and the ACM. 

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