10th IWCM Workshop Program

10th International Workshop on Compact Modeling 

January 22 (Tue), 2013 

Pacifico Yokohama, Room 419

Yokohama, Japan

Time	#	Title	Authors	Affiliation
9:00-9:10		Opening: H. J.  Mattausch (Workshop Chair)
		Power Devices   Chair: D. Navarro
9:10-9:30	1	HiSIM_HV Temperature Modeling for Multi-Geometry LDMOS: Comparison of the Temperature Flag Options	Y. Iino	Silvaco Japan
9:30-9:50	2	Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV	T. Umeda et al.	Hiroshima University
9:50-10:10	3	Floating-Base Effect Modeling for IGBT Structure using Potential Modification	T. Yamamoto et al.	Denso
10:10-10:30		- Break -
		Novel FET Structures Chair: T. Nakagawa
10:30-10:50	4	Study on Dynamic Threshold Nanowire Tunnel FET	A. Zhang et al.	Peking University Shenzhen
10:50-11:10	5	A DC Model of TFETs for SPICE Simulations	L. Zhang and M. Chan	HK UST
11:10-11:30	6	A Surface Potential Based Compact Model of Organic Thin-Film Transistor for Circuit Simulation	T.K. Maiti et al.	Hiroshima University
11:30-11:40		-  Break -
		Optical and Wireless Chair: J. He
11:40-12:00	7	An Embedded Modulation of Silicon Germanium FIN-LED - A simulation study	J. Kwon et al.	Seoul National University
12:00-12:20	8	Predicting Key Parameters of Inductive Power Links	S. Raju et al.	HK UST
12:20-14:00		- Lunch Break -
		Aging and Degradation Chair: M. Miura-Mattausch
14:00-14:40	9	Invited Keynote: Interaction of Bloch Carrier and Bound State in the Reliability Modeling	Y.J. Park and S. Choi	Seoul National University
14:40-15:00	10	Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation	C. Ma et al.	Hiroshima University, STARC
15:00-15:20	11	Effects of Nonlocal Concentration of Carriers in the Oxide for NBTI Simulation	S. Rhee et al.	Seoul National University
15:20-15:40		-  Break -
		Fabrication Variation Chair: Y. J. Park
15:40-16:00	12	Parameter Extraction for Statistical Variation of HV-MOSFETs	Y. Ueda et al.	Ricoh, STARC
16:00-16:20	13	Analysis of Gate-Length Dependence of MOSFET Random Variation by Using HiSIM-RP	S. Kumashiro et al.	Renesas Electronics
16:20-16:40	14	Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance	Y. Zhu et al.	Peking University Shenzhen
16:40-16:50		Closing: H.J. Mattausch (Workshop Chair)

IDESA Lecture

Lecture: MOSFET Modelling
J-M. Sallese; EPFL

Specific 90nm physical effects (DIBL, gate current, mobility saturation, velocity saturation). Available models and their RF performance: BSIM, EKV3, PSP. Modeling of analog and RF parameters (e.g., gm/ID, gm/gDS, CV modeling, gate leakage, etc.). Other topics include: noise modeling, distortion, breakdown effects, thermal issues and power devices, and physical layout effects (parasitics, test, maximizing gain-bandwidth, etc.). 

Location: STFC/RAL, UK; From: 14-Jan-2013 To: 18-Jan-2013

[more about IDESA Courses]

Job offer for Compact Modelling Engineer.

A job offer for compact modelling engineers, found in the web. For more information about the company, visit their website. Remember that we're not associated with them in any manner, and that we only post this as an information.

Compact Model Engineer
Reporting To: VP of Technology
Company: IO Semiconductor, Inc.
Location: San Diego, CA

Job Description and Responsibilities

• Collaborate with product development, technology development and process engineering teams on the evaluation, optimization, validation, assessment and characterization of compact device models for circuit simulation.
• Characterization and analysis of solid-state devices
• Refinement and optimization of compact models for improved analog and RF
• design efficiency and implementation on EDA platforms
• DC and RF Spice model parameter sets for typical and skewed conditions
• Device and circuit simulations
• Test structure designs for parameter extractionReports, presentations and interpretations of simulation and characterization results

Required Skills and Experience

• MS or PhD in electrical engineering, physics or equivalent
• Solid technical understanding of semiconductor device physics, device
• characterization and compact modelling for circuit simulation.
• Experience with electrical characterization, including proficiency in setting-up
• and programming measurement systems.
• Programming experience in at least one high-level, script-based language, such as
• HP Basic, Matlab or LabVIEW.
• Experience in test structure design and layout.
• Expertise in silicon-on-insulator (SOI) transistor physics and high speed device
• characterization are highly desirable.
• Experience with process and device simulation and modelling (TCAD) tools is
• desirable.
• Excellent verbal and written communication skills and a proven ability to work in
• teams.
• Excellent analytical skills
• Excellent time management and organisational skills
• A strong, hands-on individual contributor and a self-starter
• Sound communication and interpersonal skills
• Demonstrated ability to work effectively with others

[mos-ak] [on-line publications] 5th International MOS-AK/GSA Workshop in San Francisco, Dec. 12, 2012

The MOS-AK/GSA Working Group, a global compact modeling standardization forum, has delivered their 5th international compact modeling workshop, organized on Dec. 12, 2012 in the time frame of the IEDM Conference in San Francisco. The event was organized at swissnex receiving full sponsorship provided by leaders in electronic design automation including Agilent Technologies and Mentor Graphics. The FP7 COMMON Project, Eurotraining, and MOSIS Services were among the workshop technical program promoters. More than 40 international academic researchers and modeling engineers attended two sessions to hear 11 technical compact modeling talks. The session oral presentations are available for download at http://www.mos-ak.org/sanfrancisco_2012/

The compact modeling panel discussion moderated by Larry Nagel concluded the MOS-AK/GSA workshop. Invited international academic researchers and modeling engineers reviewed the status of compact modeling standardization and agreed that the Verilog-A standard offers a unique platform for compact model developments, validation, exchange and implementation into commercial as well as open source CAD/EDA tools. The panelists also pointed out the needs of further Verilog-A standard extensions and broader Verilog-AMS language definitions to better support compact device modeling, in particular focusing on Analog/RF noise applications. It is also expected that open source developers will actively contribute to standards promotion, addressing the challenges of related CAD/EDA software developments, such as Verilog-AMS debuggers supporting new model validations; and full featured, integral Verilog-AMS simulators for semiconductor device model benchmarking.

The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a spring Q2/2013 MOS-AK/GSA meeting in Munich (D), followed by a special compact modeling session at the MIXDES Conference in Gdynia (PL); and an autumn Q3/2013 MOS-AK/GSA workshop in Bucharest (RO).

Extended MOS-AK/GSA Compact Modeling Committee

[read also recent press release]

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The 20nm Moore's Law Challenge - FinFET versus SOI technology... with John Chen, Nvidia

From Electronics weSRCH:

http://electronics.wesrch.com/weqEL1UYOB

Some say Moore's Law for semiconductors has stopped. But the world of 20nm technology is coming fast.  My guest, John Chen, Vice President, Wafer Foundry Group and Global Operations of Nvidia, was here to talk about it. He talks about the strengths and weaknesses of FinFET and SOI, including the power benefits and the design challenges.  Then we examine the question of Moore's Law slowing, followed up with the need for greater collaboration between fabless and foundry in a way that looks like a Virtual IDM.

The interview is in the original link, and it's quite interesting...