IMEC presented 22nm CMOS SRAM 0.099µm2 cell:

IMEC presented the world's first functional 22nm CMOS SRAM cells made using EUV lithography. The 0.099µm² SRAM cells are made with FinFETs. In its core EC program PULLNANO, IMEC works together with leading IC companies on future CMOS technologies. Key partners in 2009 are Intel, Micron, Panasonic, Samsung, TSMC, Elpida, Hynix, Powerchip, Infineon, NXP, Qualcomm, Sony, ST Microelectronics. With such concerted collaborations, the semiconductor industry is able to keep innovating and to follow Moore's momentum, noted Luc Van den hove, COO at IMEC.

Further information on IMEC can be found at www.imec.be

IBM 28nm CMOS Technology

IBM, Chartered Semiconductor Manufacturing Ltd., GLOBALFOUNDRIES, Infineon Technologies, Samsung Electronics, Co., Ltd., and STMicroelectronics have defined and are jointly developing a 28nm, high-k metal gate (HKMG), low-power bulk CMOS process technology.

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Process for the Selection of the Next Generation Multigate Compact Models

The Compact Modeling Council (CMC) will start the process for the selection of a Multi-Gate MOSFET Compact Model with four-part standardization plan:

• Model pre-evaluation (reference data, test circuits, etc)
• Physical model accuracy evaluation
• Model functionality in IC simulation
• Formal CMC balloting

As the next steps the CMC Subcommittee finalizes process and model requirements documents, then generates data requirements document for solicit candidate models. Expect standardization effort to end by ~YE 2010.

CMOS vs. Bipolar Operational Amplifiers: Which is best for my application?

CMOS, bipolar or even BiCMOS are common process technologies used for the development of operational amplifiers, and each of these process technologies offers their own advantages and disadvantages when it comes to op amp design. Which one’s the best in terms of:

• Power Consumption
• Voltage Offset
• Noise Performance

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Process for the Selection of the Next Generation SOI MOSFET Compact Models

The Compact Modeling Council (CMC) is carrying out Process for the Selection of the Next Generation SOI MOSFET Compact Models.

The CMC is going to select SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.

The selected model developers presented their models in the to the CMC Meeting in Boston, MA on 6/5/2008.

The selected developers were : PSP-SOI-PD (for PD SOI), HiSIM SOI (for PD/DD SOI), XSIM (for DD SOI), ULTRA-SOI (for DD SOI) and PSP-SOI-DD

OKIsemi is sponsoring HiSIM SOI, FSL is sponsoring PSP-SOI-DD and IBM is sponsoring PSP-SOI-PD.

Developers are currently carrying out the required tests.