Steve Jobs promised to make #FaceTime #opensource It's time https://t.co/wSYTPTfh67 https://t.co/YT3RW26o6W

Steve Jobs promised to make #FaceTime #opensource It's time https://t.co/wSYTPTfh67 pic.twitter.com/YT3RW26o6W

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How #opensource supports #CERN's Large Hadron Collider #LHR | Tux Machines https://t.co/hqIa0aSq2f https://t.co/g9Be4iAz5P

How #opensource supports #CERN's Large Hadron Collider #LHR | Tux Machines https://t.co/hqIa0aSq2f pic.twitter.com/g9Be4iAz5P

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Digital and analog TFET circuits: Design and benchmark

Solid-State Electronics
Volume 146, August 2018, Pages 50–65
Invited Review

S. Strangio^a,b, F. Settino^a,b, P. Palestri^a, M. Lanuzza^b, F. Crupi^b, D. Esseni^a, L. Selmi^a,c

^aDPIA, Università degli Studi di Udine, Via delle Scienze 206, I-33100 Udine, UD, Italy
^bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
^cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy

ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
https://doi.org/10.1016/j.sse.2018.05.003

HIGHLIGHTS:

• We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
• Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
• Performance are evaluated down to VDD = 200 mV.
• Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.

ABSTRACT: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

FIG: Sketch of n- and p-type TFET and FinFET device architectures. The red and blue colors indicate the n- and p-doping types, respectively (green: intrinsic semiconductor, transparent-grey: oxide). TFET dimensions are: LG=20nm, nanowire cross section (LS)=7nm, EOT=1nm. FinFET dimensions are: LG=14nm, tfin=8nm, hfin=21nm, EOT=0.88nm. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

#Tesla starts to release its cars' #opensource #Linux software code https://t.co/f6Mjo1kGyn

#Tesla starts to release its cars' #opensource #Linux software code https://t.co/f6Mjo1kGyn

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15 #books for #kids who (you want to) love #Linux and #opensource https://t.co/LIRYMgXXfl https://t.co/O2D4ejSgMj

15 #books for #kids who (you want to) love #Linux and #opensource https://t.co/LIRYMgXXfl pic.twitter.com/O2D4ejSgMj

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Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples by Viera STOPJAKOVA, Matej RAKUS, Martin KOVAC, Daniel ARBET, Lukas NAGY, Michal SOVCIK, Miroslav POTOCNY https://t.co/IYoTkGeB9i #paper https://t.co/I3DD9NOApR https://t.co/jBzSISralN

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples
by Viera STOPJAKOVA, Matej RAKUS, Martin KOVAC, Daniel ARBET, Lukas NAGY, Michal SOVCIK, Miroslav POTOCNYhttps://t.co/IYoTkGeB9i #paper pic.twitter.com/I3DD9NOApR https://t.co/jBzSISralN

— Wladek Grabinski (@wladek60) May 23, 2018

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Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples by Viera STOPJAKOVA, Matej RAKUS, Martin KOVAC, Daniel ARBET, Lukas NAGY, Michal SOVCIK, Miroslav POTOCNY https://t.co/IYoTkGeB9i #paper https://t.co/I3DD9NOApR

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples
by Viera STOPJAKOVA, Matej RAKUS, Martin KOVAC, Daniel ARBET, Lukas NAGY, Michal SOVCIK, Miroslav POTOCNYhttps://t.co/IYoTkGeB9i #paper pic.twitter.com/I3DD9NOApR

— Wladek Grabinski (@wladek60) May 23, 2018

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[mos-ak] [Final Program] 3rd Sino MOS-AK Compact Modeling Workshop in Beijing, June 14-16 2018

3rd Sino MOS-AK Compact Modeling Workshop

http://www.mos-ak.org/beijing_2018

Beijing, June 14-16 2018

Final Program 

Together with Professor Yan Wang, Tsinghua University, Honorary Committee; George Ponchak, T-MTT Editor and Yuhua Cheng, PKU, Advisory Committee as well as Min Zhang, XMOD, Organizing Committee General Co-Chair, we have pleasure to invite to the 3rd Sino MOS-AK Compact Modeling Workshop which will be organized successively in China between June 14-16, 2018

Scheduled,3rd subsequent MOS-AK modeling workshop organized in China, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:

http://www.mos-ak.org/beijing_2018

3rd Sino MOS-AK Compact Modeling Workshop program includes: 

Day 1 (June 14): MOS-AK Tutorial Day

Day 2 (June 15): MOS-AK SPICE/Verilog-A Modeling Workshop

Day 3 (June 16): MOS-AK SPICE/Verilog-A Modeling Workshop

Venue: 

Tsinghua University

会议场所：清华大学FIT-楼，在紫光国际国际交流中心旁

close to Tsinghua Unisplendour International Center

Online Workshop Registration is still open

(any related inquiries can be sent to register@mos-ak.org)

Workshop Secretary:

Li Zhang
Office: +86 010 62771733;Mobile: +86 138 01302877
Email: zhangli95@tsinghua.edu.cn

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

International MOS-AK Committee

WG190518

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Advanced #FDSOI Device Design: The U-Channel Device for #7nm Node and Beyond https://t.co/fGaY4WQbu2 #paper

Advanced #FDSOI Device Design: The U-Channel Device for #7nm Node and Beyond https://t.co/fGaY4WQbu2 #paper

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Universal Core #Model for Multiple-gate Field-effect Transistors with Short Channel and Quantum Mechanical Effects - IOPscience https://t.co/vDJ9kII7pm https://t.co/vDJ9kII7pm

Universal Core #Model for Multiple-gate Field-effect Transistors with Short Channel and Quantum Mechanical Effects - IOPscience https://t.co/vDJ9kII7pm https://t.co/vDJ9kII7pm

— Wladek Grabinski (@wladek60) May 2, 2018

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Universal Core #Model for Multiple-gate Field-effect Transistors with Short Channel and Quantum Mechanical Effects - IOPscience https://t.co/vDJ9kII7pm

Universal Core #Model for Multiple-gate Field-effect Transistors with Short Channel and Quantum Mechanical Effects - IOPscience https://t.co/vDJ9kII7pm

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A Physics-Based Compact #Model for Transition-Metal Dichalcogenides Transistors With the Band-Tail Effect - IEEE Journals & Magazine https://t.co/vJ0ZNcV7zw https://t.co/vJ0ZNcV7zw

A Physics-Based Compact #Model for Transition-Metal Dichalcogenides Transistors With the Band-Tail Effect - IEEE Journals & Magazine https://t.co/vJ0ZNcV7zw https://t.co/vJ0ZNcV7zw

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A Physics-Based Compact #Model for Transition-Metal Dichalcogenides Transistors With the Band-Tail Effect - IEEE Journals & Magazine https://t.co/vJ0ZNcV7zw

A Physics-Based Compact #Model for Transition-Metal Dichalcogenides Transistors With the Band-Tail Effect - IEEE Journals & Magazine https://t.co/vJ0ZNcV7zw

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Symposium on Schottky Barrier MOS Devices 2018

"devil of savior"

It is the 40th anniversary of Institut für Halbleitertechnik und Nanoelektronik (IHTN) of the TU Darmstadt, Germany. In addition to many activities in September, a small symposium on Schottky Barrier MOS (SB-MOS) devices is planned for August 7th in Darmstadt. This is the second meeting of an enthusiastic group of Schottky barrier researchers and this year it is sponsored by the EDS German chapter and hosted by the IHTN of TU Darmstadt.

This year the symposium is organized by Dr. Tillmann Krauss, Dr. Udo E. Schwalke, Dr. Mike Schwarz and the staff of the TU Darmstadt. The symposium starts at 11:00 am in the lecture hall at the ITHN TU Darmstadt. 

The following agenda is planned:






AGENDA:

11:00 – 11:15 Welcome and introduction by Prof. Schwalke
11:15 – 11:30 “Wrap-Up of Schottky Barrier Simulation Methodologies”, Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM) (15mins)
11:30 – 12:00 “DC/AC compact modeling of Tunnel-FETs”, Prof. Alexander Kloes (NanoP THM) (30mins)
12:00 – 12:30 “Benefits of Schottky Barrier vs. Conventional Doped Source/Drain MOS devices”, Dr. John Snyder (JCap, LLC) (30mins)
12:30 – 13:30 “Lunch”
13:30 – 14:00 “Nanowire Schottky devices”, Dr. Walter Weber (TU Dresden) (30mins)
14:00 – 14:30 “Nanoelectronics: From Silicon to Carbon”, Prof. Udo Schwalke (TU Darmstadt) (30mins)
14:30 – 14:45 “Coffee Break”
14:45 – 15:15 “Transfer-free fabrication of nanocrystalline graphene field-effect sensors”, Dennis Noll (TU Darmstadt) (30mins)
15:15 – 15:45 “Modeling of neuromorphic devices”, Dr. Laurie E. Calvet (Université Paris-Sud) (30mins)

Attendees are welcome to attend the symposium. Further information are present at http://www.iht.tu-darmstadt.de/ihtn_institute/

Manchester thin-film #oxide #IGZO #transistor hits 1GHz https://t.co/W8DwPti37u #paper

Manchester thin-film #oxide #IGZO #transistor hits 1GHz https://t.co/W8DwPti37u #paper

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Performance Potential of #Ge #CMOS Technology From a Material-Device-Circuit Perspective https://t.co/cSWOhx5xSn #paper

Performance Potential of #Ge #CMOS Technology From a Material-Device-Circuit Perspective https://t.co/cSWOhx5xSn #paper

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Subthreshold Modeling of TriGate Junctionless Transistors With Variable Channel Edges & Substrate Bias Effects https://t.co/ZScVIyoP3k #paper https://t.co/ZScVIyoP3k

Subthreshold Modeling of TriGate Junctionless Transistors With Variable Channel Edges & Substrate Bias Effects https://t.co/ZScVIyoP3k #paper https://t.co/ZScVIyoP3k

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Compact Drain Current #Model for #TFT Under Bias Stress Condition https://t.co/t8RWZbee7Z

Compact Drain Current #Model for #TFT Under Bias Stress Condition https://t.co/t8RWZbee7Z

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[Extended Deadline] Special IEEE TED Issue on “Compact Modeling for Circuit Design"

Call for papers for 

Special IEEE TED Issue

on

Compact Modeling for Circuit Design

Extended deadline: May 15, 2018               Publication date: January 2019

In order to capture the full potential of semiconductor devices, compact device models and design software are critically needed. Predictive and physical device and circuit design software are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate device models, and for circuit design, compact models.

In particular, compact device models are the vehicle that allows the design of circuits using the targeted devices. The compact model should not only accurately capture the physics of the device in all operation regimes, but at the same time should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. On the other hand, compact models can also be used as a tool to make clear estimations and predictions of the performances of future devices following technological trends. The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical mechanisms that govern their behaviours. Regarding many emerging non-silicon structures, devices, circuit and system designers very often rely on empirical behavioural macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, nor the quantitative predictive quality required for the accurate production quality design.

Therefore, the main objective of this dedicated special issue is to engage Electron Devices Community in a serious discussion with their scholarly contributions specifically focused on solving major challenges in the broad area of compact device modeling for circuit design.

Suggested topics include but not limited to:

1. Silicon MOSFET modeling: Advanced Bulk MOSFETs; SOl MOSFETs; Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, UTB SOI MOSFETs; Junctionless MuGFETs; Power and High Voltage MOSFETs.
2. Junction-based and compound semiconductor FET modeling: Advanced MESFETs; Advanced HEMTs; lIl-V and Ill-N; MOSFETs; Advanced IFETs.
3. Diode and bipolar transistor modeling: Advanced BJTs; HBTs; IGBTs; pn and pin diodes; Varactors.
4. Emerging transistor modeling: Tunnel FETs; Molecular transistors; Single Electron Transistors; Quantum Dot Transistors; Negative Capacitance Transistors.
5. Emerging semiconductor devices: Memories, MRAM, PCRAM etc.; Spintronic devices; Layered/2D materials
6. Thin-Film FETS (TFT): a-Si:H TFTs; Polycrystalline Si TFTs; OTFTs and OECTs; Oxide TFTs; Single-crystal TFTs.
7. Modeling of physical effects: Noise; High frequency operation; Mismatch; Strain; High energy particle interactions in ICs (Cosmic rays and energy beams); ESD events; Ballistic and quasi-ballistic transport; Layout dependent effects.
8. Photonic devices: LEDs and OLEDs; Photodiodes; Solar cells; Photodetectors; SPADs.
9. Model implementation in EDA tools and applications: Model code adaptation to EDA tools; Computational model performances in design tools; Challenges of model implementation in design tools; Compact model applications to variation and statistical analysis; Compact model applications to thermal analysis; Compact model applications to design exploration; Compact model applications to design optimization; Compact model applications to device process improvements; Compact modeling for BSD prediction; Circuit design using new compact models.

Submission instructions: Manuscripts should he submitted in a double column format using an IEEE style file Please visit the following link to download the templates:

http://www,ieeeiorg/publicationsistandards/publications/authors/author7templates,html

In your cover letter, please indicate that your submission is for this special issue. Please submit papers using the website: http://mc.manuscriDtcentral.com/ted

Guest Editors:

1. Benjamin Iniguez, URV, Tarragona (SP) Editor-in-Chief
2. Yogesh Chauhan, IIT Kanpur (IN)
3. Andries Scholten, NXP Semiconductors, Eindhoven (NL)
4. Ananda Roy, Intel Corporation, Portland, OR (USA)
5. Slobodan Mijalkovic, Silvaco Europe Ltd, St. Ives (UK)
6. Sadayuki Yoshitomi, Toshiba Corporation, Tokyo (J)
7. Kejun Xia, NXP Semiconductors, Phoenix, AZ (USA)
8. Wladek Grabinski, GMC Consulting, Commugny (CH)
9. Kaikai Xu, UEST of China, Chengdu (CN) 

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Direct Measurement of Active Near-Interface Traps in the Strong-Accumulation Region of 4H- #SiC #MOS Capacitors https://t.co/e0jNWoZfQn #paper https://t.co/e0jNWoZfQn

Direct Measurement of Active Near-Interface Traps in the Strong-Accumulation Region of 4H- #SiC #MOS Capacitors https://t.co/e0jNWoZfQn #paper https://t.co/e0jNWoZfQn

— Wladek Grabinski (@wladek60) April 20, 2018

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Book Performance Report 2017/18

(as of April 2018)

POWER/HVMOS Devices Compact Modeling
Editors: Grabinski, Wladyslaw, Gneiting, Thomas (Eds.)
ISBN 978-90-481-3046-7 (ebook)
ISBN 978-90-481-3045-0 (print book)

Availability of and results for eBook Since its online publication on February 25, 2010, there has been a total of 5,796 chapter downloads for eBook on SpringerLink. The table to the right shows the download figures for the last year(s). In addition to the collections, Springer eBooks are available for individual use from our web shop. The book can be ordered/downloaded directly from its home page.  MyCopy: book is available as a MyCopy version, which is a unique service that allows library patrons to order a personal, printed-on-demand softcover edition of an eBook for just $/€24.99.  To further widen the distribution of eBook, it has also been made available in the following shop(s): Amazon Kindle Shop Apple iTunes Google play eBooks reach a broad readership and provide global visibility for the book. Spreading the word about the book To present the book POWER/ HVMOS Devices Compact Modeling to its potential readers and make it findable by search engines, it has its own home page, which can be shared through social media and where you can download a flyer for the book! In 2017 this page was visited 112 times.  The book has been announced by the New Book Alert, our largest customer emailing.  Journal editors, journalists or bloggers can request a free Online Review Copy of the book from its home page. This online service makes it especially easy for them to write a review. All potencial, reviews can be an excellent way to boost a book’s visibility in the relevant communities and raise reader interest!

Year Chapter Downloads 2017 766 2016 843 2015 912 2014 1,333 2013 658 2012 420 2011 401 2010 463

EDS DL MQ Gdynia Maritime University, June 20, 2018, Gdynia, Poland

EDS Distinguished Lecturer Mini-Colloquium
SiC: technology, devices, modeling
Gdynia Maritime University, June 20, 2018, Gdynia, Poland
admission: free of charge

organized by:	ED Poland Chapter Gdynia Maritime University Instytut Technologii Elektronowej (ITE, Warsaw)
technical support:	Lodz University of Technology, Department of Microelectronics and Computer Science
venue:	Gdynia Maritime University ul. Morska 83, 81-225 Gdynia, Poland

9:00-9:05

Introduction

Dr. Daniel Tomaszewski, IEEE EDS Member, ITE, Warsaw

9:05-9:50 SiC technology offerings; challenges and opportunities

Lecturer: Dr. Muhammad Nawaz, IEEE Senior Member, IEEE EDS Distinguished Lecturer,
ABB Corporate Research, Sweden

Abstract: A wide bandgap SiC technology has now entered in transitional phase on various power electronics front; thanks to its superior physical properties such as wide bandgap, larger breakdown field strength, higher carrier saturation velocity, and larger thermal conductivity than that of Si counterpart. Low voltage SiC MOSFET discrete devices and power modules within voltage range of 1.2-1.7 kV are commercially available. On the other side, medium voltage MOSFET devices of 3.3-6.5 kV and high voltage MOSFET devices of 10-15 kV are also visible in the scientific literature with excellent static and dynamic performance, illustrating the potential benefit for high power applications in energy transmission and distribution networks. This talk will focus on the requirement and issues using SiC MOSFETs facing high power applications while addressing simultaneously the potential benefits for high power converters. Reliability concerns from the end user’s perspective will be addressed as well.

10:00-10:45 On the way to the Energy and Variability Efficient (E.V.E.) Era

Lecturer: Prof. Simon Deleonibus, IEEE Fellow, IEEE EDS Distinguished Lecturer, Fellow Electrochemical Society, CEA Research Director, France

Abstract: Major power consumption reduction will drive future design of technologies and architectures that will request less greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-dimensional integration of hybrid, heterogeneous technologies at the device, functional and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co integrated Low Power and High Performance Logic and Memory devices.The future of Nanoelectronics will face the major concerns of being Energy and Variability Efficient (E.V.E.).

10:55-11:15 Coffee break

11:15-12:00 SiC power device fabrication and path to commercialization

Lecturer: Prof. Victor Veliadis, IEEE Fellow, IEEE EDS Distinguished Lecturer, Deputy Executive Director and CTO, PowerAmerica Professor of Electrical and Computer Engineering, North Carolina State University

Abstract: The presentation will discuss major SiC power device application areas and touch on foundry models, cost reduction strategies, and path to commercialization. The advantages of SiC over other power electronic materials will be outlined, and SiC devices currently developed for power electronic applications will be introduced. Emphasis will be placed on SiC MOSFETs, which are currently being inserted in the majority of SiC based power electronic systems. Aspects of device fabrication will be given, with stress on processes that do not carry over from the mature Si manufacturing world and are thus specific to SiC. Finally, the presentation will highlight common SiC Edge Termination techniques, which allow devices to reach their full high-voltage potential.

12:10-12:55 The importance of the diffusion currents in the photoelectric investigations of the MIS system

Lecturer: Prof. Henryk M. Przewłocki, IEEE Senior Member, IEEE EDS Distinguished Lecturer, Instytut Technologii Elektronowej (ITE Warsaw), Poland

Abstract: The fundamental property of any nanoelectronic material or system is its energy band diagram, which allows to predict its physical properties, potential applications and/or limitations. The most effective methods of band diagram determination are the photoelectric methods, which deserve therefore detailed theoretical analysis, as well as precisely controlled experimental procedures. It is shown in this paper that the commonly accepted and currently applied theory (further called classical theory) of internal photoemission in the metal-insulator-semiconductor (MIS) system, which very well represents its experimental characteristics taken at high enough electric fields E, in the insulator, fails at low electric fields (usually for E < (104-105) V/cm), i.e. in the vicinity of the point where the photocurrent changes sign (I=0). This failure of the classical theory will be demonstrated by comparing the characteristics calculated using the classical theory with the experimental characteristics taken in the range of low electric fields in the insulator. It was already shown some time ago, by the present author that this discrepancy results from the neglect of the diffusion currents, which become important at low electric fields in the insulator. In this paper the origin, the magnitude and the role of diffusion current in determination of the MIS system photoelectric characteristics at low electric fields in the insulator will be quantitatively analyzed. The theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account will be presented. It will be shown that characteristics calculated using this theory remain in good agreement with the relevant experimental characteristics. The ability to accurately predict these characteristics in the range of low electric fields opens the possibilities of developing new measurement methods of the MIS system crucial parameters. Examples of such methods will be demonstrated.

13:05-14:05 Lunch Break

14:05-14:50 Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools

Lecturer: Prof. Mike Brinson, Fellow of the IET, CEng., Member of the Institute of Physics, CPhys. Centre for Communications Technology, London Metropolitan University, UK

Abstract: The purpose of this presentation is provide an overview of the fundamentals of the Verilog-A hardware description language and its use in compact modelling of established and emerging semiconductor technology devices. With the adoption of Verilog-A as the standardised model interchange language by CMC, a knowledge of this subject is of increasing importance to the modelling community. Similarly, access to freely available Verilog-A modelling tools and circuit simulators is essential if Verilog-A modelling techniques are to be widely adopted. For this reason, in an attempt to encouraging all who attend to experiment with Verilog-A. the presentation is based on the Qucs-S, QucsStudio and the MAPP/Octave FOSS software. Throughout the talk a series of modelling case studies outline the stages in the development of Verilog-A models for established and SiC semiconductor devices. In the later stages of the presentation participants are also introduced to using the Berkeley MAPP tools with Qucs-S/Xyce.

15:00-15:45 FOSS TCAD/EDA Tools for Advanced Compact Modeling

Lecturer: Dr. Wladek Grabinski, IEEE Senior Member, IEEE EDS Distinguished Lecturer, MOS-AK (EU), Switzerland

Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

15:55 End of MQ

Semianalytical #modeling of the depletion layers and their effects on the #threshold #voltage of a #junctionless double‐gate MOSFET including trapped charges - Beigi - - IJNM - Wiley Online Library https://t.co/P6T6PSop2t https://t.co/P6T6PSop2t

Semianalytical #modeling of the depletion layers and their effects on the #threshold #voltage of a #junctionless double‐gate MOSFET including trapped charges - Beigi - - IJNM - Wiley Online Library https://t.co/P6T6PSop2t https://t.co/P6T6PSop2t

— Wladek Grabinski (@wladek60) April 17, 2018

from Twitter https://twitter.com/wladek60

April 17, 2018 at 11:16PM
via IFTTT

A scalable and multibias #parameter #extraction method for a small‐signal GaN HEMT #model - Chen - - International Journal of Numerical Modelling: Electronic Networks, Devices and Fields - Wiley Online Library https://t.co/qStCsViVKt https://t.co/qStCsViVKt

A scalable and multibias #parameter #extraction method for a small‐signal GaN HEMT #model - Chen - - International Journal of Numerical Modelling: Electronic Networks, Devices and Fields - Wiley Online Library https://t.co/qStCsViVKt https://t.co/qStCsViVKt

— Wladek Grabinski (@wladek60) April 17, 2018

from Twitter https://twitter.com/wladek60

April 17, 2018 at 10:20PM
via IFTTT

#Graphene is Grown With the Same Band Gap as #Silicon - IEEE Spectrum #paper https://t.co/Cxv8s8DKef

#Graphene is Grown With the Same Band Gap as #Silicon - IEEE Spectrum #paper https://t.co/Cxv8s8DKef

— Wladek Grabinski (@wladek60) April 16, 2018

from Twitter https://twitter.com/wladek60

April 16, 2018 at 10:36PM
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A new approach to the extraction of single exponential diode #model parameters https://t.co/qc5i9xwEwK

A new approach to the extraction of single exponential diode #model parameters https://t.co/qc5i9xwEwK

— Wladek Grabinski (@wladek60) April 14, 2018

from Twitter https://twitter.com/wladek60

April 14, 2018 at 03:33PM
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Using #opensource Designs to Create More Specialized #IC. RISC-V wants to do for chips what Linux did for software. https://t.co/M9iVOgdb7k https://t.co/JyDdsDs7Pb https://t.co/VrKNjBxkmt

Using #opensource Designs to Create More Specialized #IC. RISC-V wants to do for chips what Linux did for software. https://t.co/M9iVOgdb7k pic.twitter.com/JyDdsDs7Pb https://t.co/VrKNjBxkmt

— Wladek Grabinski (@wladek60) April 13, 2018

from Twitter https://twitter.com/wladek60

April 13, 2018 at 04:30PM
via IFTTT

RG: article reached 2,000 reads

Article reached 2,000 reads: Open-source circuit simulation tools for RF compact semiconductor device modelling

Detailed characterisation of #Si Gate-All-Around #Nanowire MOSFETs at #cryogenic temperatures https://t.co/Zk7A4wLWM2 #paper https://t.co/n08yBDhilP https://t.co/7WRK6MnPkB

Detailed characterisation of #Si Gate-All-Around #Nanowire MOSFETs at #cryogenic temperatures https://t.co/Zk7A4wLWM2 #paper pic.twitter.com/n08yBDhilP https://t.co/7WRK6MnPkB

— Wladek Grabinski (@wladek60) April 10, 2018

from Twitter https://twitter.com/wladek60

April 10, 2018 at 05:06PM
via IFTTT

Analysis and modeling of #wafer-level process #variability in #28nm #FDSOI using split C-V measurements https://t.co/M8lmHyZUgN #paper https://t.co/EGJ0xYgMml https://t.co/xHtRIxYSpG

Analysis and modeling of #wafer-level process #variability in #28nm #FDSOI using split C-V measurements https://t.co/M8lmHyZUgN #paper pic.twitter.com/EGJ0xYgMml https://t.co/xHtRIxYSpG

— Wladek Grabinski (@wladek60) April 9, 2018

from Twitter https://twitter.com/wladek60

April 09, 2018 at 05:40PM
via IFTTT

Low voltage operation of #GaN vertical #nanowire #MOSFET https://t.co/jAwjUJ6I7j #paper https://t.co/3zRydkWQWy

Low voltage operation of #GaN vertical #nanowire #MOSFET https://t.co/jAwjUJ6I7j #paper pic.twitter.com/3zRydkWQWy

— Wladek Grabinski (@wladek60) April 9, 2018

from Twitter https://twitter.com/wladek60

April 09, 2018 at 05:36PM
via IFTTT

[mos-ak] [2nd Announcement and Call for Papers] 3rd Sino MOS-AK Workshop Peking, June 14-16 2018

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

3rd Sino MOS-AK Workshop

Peking, June 14-16 2018

Together with the Honorary Committee Chair, Yan Wang, Tsinghua University, local organization team and International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 3rd Sino MOS-AK Compact/SPICE Modeling Workshop which will be organized at Tsinghua University between June 14-16, 2018.

Planned 3rd Sino MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue: 

会议场所：清华大学FIT-楼，在紫光国际国际交流中心旁
Tsinghua University FIT building, close to Tsinghua Unisplendour International Center

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Speakers: Invited talks tentative listing (alphabetic order)

• Prof. Mansun Chan; Compact Models for Giga-Scale Memory System
  
• Dr. Axel Huelsmann; mHEMT based MMICs, Modules, and Systems for mmWave Applications
  
• Dr.-Ing. Franz Sischka; Successful and Verified RF Measurements for Device Modeling
  
• Dr. Lifeng Wu; A Full Design Flow Solution for OLED Flat Panel Display
  
• Dr. Pete Zampardi; Understanding Gaps in III-V HBT Modeling and Simulation
  

Important Dates: 

• Call for Papers - March 2018
  
• 2nd Announcement - April 2018
  
• Final Workshop Program - May 2018
  
• MOS-AK Workshop - June 14-16 2018
  
• Day 1: MOS-AK Tutorial Day
  
• Day 2: MOS-AK SPICE/Verilog-A Modeling Workshop
  
• Day 3: MOS-AK SPICE/Verilog-A Modeling Workshop
  

Online Abstract Submission is open 

(any related enquiries can be sent to abstract@mos-ak.org)

Manuscript submission deadline: 28th May 2018 (Monday)

Notification of Acceptance: 4th June 2018 (Monday)

Submission of final manuscript: 11th June 2018 (Monday)

Online Workshop Registration is open 

(any related enquiries can be sent to registration@mos-ak.org)

Postworkshop IJHSES Publications:

Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

International MOS-AK Committee:

• Honorary Committee Chair
• Yan Wang, Tsinghua University
• Advisory Committee
• George Ponchak, T-MTT Editor
• Yuhua Cheng, PKU
  
• Organizing Committee General Co-Chairs:
• Min Zhang, XMOD Technologies
• Wladek Grabinski, MOS-AK (EU)
• Finance Chair:
• Li Zhang, Tsinghua University
• Publication Chair: 
  
• Wladek Grabinski, MOS-AK (EU)
• Awards Committee Chair:
• Zhiping Yu, Stanford University
• Sponsorship Chair:
• Li Zhang, Tsinghua University
• Min Zhang, XMOD Technologies
• Exhibition Chair:
• Jin Chen, SIMIT
• Kai Lv, NUS
• Local Arrangements Chair:
• Wenfei Hu, Tsinghua University
• Publicity:
• Sen Yin, Tsinghua  University
• Workshop Secretary:
• Li Zhang
• Office: +86 010 62771733; 
• Mobile: +86 138 01302877
• Email: zhangli95@tsinghua.edu.cn

Extended MOS-AK Committee

WG03043018

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