[paper] Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325 GHz

Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325GHz

Marina Deng^a, Thomas Quémerais^b, Simon Bouvot^a, ^b, Daniel Gloria^b, Pascal Chevalier^b

Sylvie Lépilliet^a, François Danneville^a, Gilles Dambrine^a

^aIEMN UMR CNRS 8520, University of Lille, Avenue Poincaré, CS60069, 

59652 Villeneuve-d’Ascq Cedex, France

^bSTMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France

Highlights

• The SiGe HBT full S-parameters from 250MHz to 325GHz under multiple bias conditions are presented for the first time.
• Standard calibration and de-embedding techniques are used and remained valid up to 325GHz thanks to a reduction of the test structures dimensions.
• A simple and accurate small-signal electrical model was extracted and compared with measurements up to 325GHz.

Received 19 September 2016, Revised 18 November 2016, Accepted 21 November 2016, Available online 22 November 2016 [read more...]

http://dx.doi.org/10.1016/j.sse.2016.11.012

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 

INFOS 2017

June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:

• High-k dielectrics, metal gate materials and SiO2 for future scaling
• Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
• Stacked dielectrics for non-volatile memory (flash, nc-Si)
• Dielectrics for resistive switching memories and spin memories
• Dielectrics for DRAM and MIM
• Low-k dielectrics
• Semiconductors on insulators
• Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
• Surface cleaning technologies
• Physics and chemistry of dielectrics and defects
• Characterization techniques for dielectrics and interfaces
• Electrical reliability, leakage and modelling
• Modelling of atomic structure of dielectrics, interfaces and thin films
• Topological insulators
• Ferroelectrics and functional oxides
• Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
• Dielectrics for photonics and sensing

AMS Multi Project Wafer Service

AMS MPW Service:

ams' Multi Project Wafer (MPW) service, also known as shuttle runs, is a fast and cost-efficient prototyping service, which combines several designs from different customers onto a single wafer.

ams’ best in class MPW service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants. It includes the whole range of 0.18µm and 0.35µm specialty processes:

• CMOS Mixed Signal
• CMOS Mixed Signal with embedded EEPROM
• CMOS High Voltage (up to 120 Volts)
• CMOS High Voltage with embedded EEPROM
• CMOS Opto
• SiGe-BiCMOS

The complete MPW schedule including detailed start dates per process is available on the web at http://asic.ams.com/MPW

Deliverables: Participating the ams MPW service includes the delivery of 40 prototypes for design verification. Packaged engineering samples are offered within 2 days (ceramic) and 3 weeks (plastics) cycle time, respectively. The total turnaround time from MPW deadline to delivery is app. 8 weeks (CMOS). Overall, ams offers almost 150 MPW start dates in 2016 and 2017, enabled by long lasting co-operations with partner organizations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies [read more...]