[C4P] LAEDC 2024

CALL FOR PAPERS & POSTERS

LAEDC 2024 R&D topics of interest include, but are not limited to:

All electron-based devices Electron Devices for Quantum Computing RF-MMW-5G Semiconductor-, MEMS- and Nanotechnologies Packaging, 3D integration Sensors and actuators Display technology Modeling and simulation Reliability and yield Device characterization Reliability Agrivoltaics

Flexible electronics Biomedical Devices Circuit-device interaction Novel materials and process modules Technology roadmaps Electron device engineering education Electron device outreach Optoelectronics, photovoltaic and photonic devices and systems Humanitarian Projects STEM Initiatives Energy harvesting 2D Materials and Devices

IMPORTANT DATES:

• Paper submission deadline: January 15, February 19, 2024
• Author notification: April 1, 2024
• LAEDC Conference Dates: MAY 8-10 2024

SPECIAL SESSIONS:

• MOS-AK Workshop
• IEEE EDS MQ
• LAEDC Summer School
• IEEE WIE/YP Session
• Humanitarian Technology Session

ABOUT GUATEMALA:

Guatemala, country of Central America. The dominance of an Indigenous culture within its interior uplands distinguishes Guatemala from its Central American neighbours. The origin of the name Guatemala is Indigenous, but its derivation and meaning are undetermined. Some hold that the original form was Quauhtemallan (indicating an Aztec rather than a Mayan origin), meaning “land of trees,” and others hold that it is derived from Guhatezmalha, meaning “mountain of vomiting water” - referring no doubt to such volcanic eruptions as the one that destroyed Santiago de los Caballeros de Guatemala (now Antigua Guatemala), the first permanent Spanish capital of the region’s captaincy general. The country’s contemporary capital, Guatemala City, is a major metropolitan centre. Quetzaltenango, in the western highlands, is the nucleus of the Indigenous population.

Chipsalliance Technology Update - Nov. 2023

November 9, 2023

Check out the presentations below, and watch the replay here

• Project Open Se Cura (slides)
  Kenny Vassigh, Bangfei Pan, Cindy Liu, Kai Yick, Google, Michael Gielda, Antmicro, Brian Murray, Verisilicon
• Caliptra Workgroup Update (slides)
  Andres Lagar-Cavilla, Google
• Enabling UVM testbenches in Verilator (slides)
  Michael Gielda, Karol Gugala, Antmicro
• FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development (slides)
  Olof Kindgren, Qamcom
• CHIPYard: An Open Source RISC-V Design Framework (slides)
  Sagar Karandikar, U.C. Berkeley

Watch the Replay

[paper] Boropheneand Metal Interface

Vaishnavi Vishnubhotla, Sanchali Mitra, and Santanu Mahapatraa

First-principles based study of 8-Pmmn boropheneand metal interface

J. Appl. Phys. 134, 034301 (2023); doi: 10.1063/5.0144328

DOI 10.1063/5.0144328

Nano-Scale Device Research Laboratory, Department of Electronic Systems Engineering, 

Indian Institute of Science (IISc) Bangalore, India

Abstract: Borophene, the lightest member of mono-elemental 2D materials family, has attracted much attention due to its intriguing polymorphism. Among many polymorphs, digitally discovered 8-Pmmn stands out owing to its unique tilted-Dirac fermions. However, the property of interfaces between 8-Pmmn and metal substrates has so far remained unexplored, which has critical importance of its application in any electronic devices. Here, with the help of density functional theory, we show that the unique tilted-Dirac property is completely lost when 8-Pmmn borophene is interfaced with common electrode materials such as Au, Ag, and Ti. This is attributed to the high chemical reactivity of borophene as observed from crystal orbital Hamilton population and electron localization function analysis. In an effort to restore the Dirac property, we insert a graphene/hexagonal-boron-nitride (hBN) layer between 8-Pmmn and metal, a technique used in recent experiments for other 2D materials. We show that while the insertion of graphene successfully restores the Dirac nature for all three metals, hBN fails to do so while interfacing with Ti. The quantum chemical insights presented in this work may aid in to access the Dirac properties of 8-Pmmn in experiments.

FIG: (a) Top and side views of 3 × 3 × 1 supercell of 8-Pmmn borophene. The lattice parameters are a = 3.26 Å, b = 4.52 Å, and h = 2.19 Å. The inner and ridge atoms are denoted by blue and green atoms, respectively. (b) Crystal orbital Hamilton population (COHP) analysis and (c) electron localization function (ELF) plot for graphene and 8-Pmmn borophene.

Acknowledgments: The authors acknowledge the Supercomputer Education and Research Center (SERC), Indian Institute of Science (IISc), Bangalore, for CPU- and GPU-based computations. The computational charges were aided by the Mathematical Research Impact Centric Support (MATRICS) scheme of Science and Engineering Research Board (SERB), Government of India, under Grant No. MTR/2019/000047.

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

Cutting-Edge IC Design Workshop

U.S. - Japan Collaboration Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM  (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST) 

Online

The semiconductor industry is facing a number of challenges in building a stable supply chain. The importance of semiconductors was reaffirmed at the global level, and various initiatives were announced to revitalize and support the semiconductor industry, including investment in infrastructure development and human resource development for cutting-edge foundries. Against this backdrop, it is hoped that the creation of next-generation semiconductor technology and the further expansion of the industry will be achieved based on strong cooperation between Japan and the United States. As a phase 1 toward this goal, this workshop will discuss cutting-edge IC design technologies such as open source IC design, ecosystem construction, and human resource development. This workshop was supported by the U.S. Consulate in Fukuoka.

Application deadline is December 12. Please apply individually for DAY-1 and DAY-1the following form (you can also apply for only one of them).

• DAY-1 Application (Click here)
• DAY-2 Application (Click here)

[Participation fee] Free

[Notice] Simultaneous interpretation is available in English and at ZOOM Webinar.

DAY-1: Dec. 5th, 8:00-11:35 AM (JST)

8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

8:05 - 8:10 Welcome Remarks from the U.S. Consulate in Fukuoka

8:10 - 8:40 TBD, Steve Kosier, Skywater

8:40 - 9:10 The Emerging Ecosystem of Open-Source IC Design: IEEE SSCS Activities and Future Goals, Boris Murmann, Chair of the SSCS TC OSE, University of Hawaii

9:10 - 9:40 Human resource development for Semiconductor Technologies in Fukuoka, Koji Inoue, Fukuoka Semiconductor Reskilling Center/Kyushu University, Hideharu Kanaya, Kyushu University,

9:40 - 9:50 Break

9:50 - 10:20 Lab to Fab in the Cloud: Semiconductor Innovation at Amazon, David Pellerin, AWS 

10:20 - 10:50 TBD, Kai Yick, Google Research ML

10:50 - 11:20 Analog and Mixed-Signal IC Design Automation, David Wentzloff, University of Michigan

11:20 - 11:30 Q&A + Panel Discussion

11:30 - 11:35 Conclusion, Mehdi Saligane, University of Michigan

DAY-2: Dec. 6th, 8:00-11:30 AM (JST)

8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

8:05 - 8:35 Innovation by Collaboration: CHIPS Alliance, Rob Mains, CHIPS Alliance, Linux Foundation 

8:35 - 9:05 Developing CMOS+X Platforms for Artificial Intelligence and Beyond, Brian Hoskins, NIST 

9:05 - 9:35 Agile-X: Agile Chip Design and Fabrication Platform, Makoto Ikeda, University of Tokyo

9:35 - 9:45 Break

9:45 - 10:15 The future of semiconductor : chips and chiplets, Dan J. Dechene, IBM Research

10:15 - 10:45 AI Chip Design Center – open hub for chip innovation -, Kunio Uchiyama, National Institute of Advanced Industrial Science and Technology  

10:45 - 11:15 Democratizing EDA Tooling and Chip Design, Johan Euphrosine, Google (Tentative)

11:15 - 11:25 Q&A + Panel Discussion

11:25 - 11:30 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

[お問い合わせ] ic-design-ws 'at' slrc.kyushu-u.ac.jp　（ 'at' を @ で置き換えてください）