[paper] eSim: An Open Source EDA Tool

Rahul Paknikar, Saurabh Bansode, Gloria Nandihal, Madhav P. Desai, Kannan M. Moudgalya, 

and Ashutosh Jha*

eSim: An Open Source EDA Tool for Mixed-Signal and Microcontroller Simulations

4th International Conference on Circuits, Systems and Simulation

(ICCSS), 2021, pp. 212-217,

DOI: 10.1109/ICCSS51193.2021.9464198.

Indian Institute of Technology Bombay, Mumbai, Maharashtra, India
* Vellore Institute of Technology Chennai, Tamil Nadu, India

Abstract: The ability to carry out simulations before making a PCB can save a lot of time, effort and cost. This work explains the creation of an open source mixed-signal simulation software eSim that will be of great help to students, hobbyists, the SME sector and startups. Analog and digital components are respectively modelled using SPICE and a hardware descriptive language in eSim. Inclusion of AVR based microcontroller as a part of the digital circuit is demonstrated through its instructions implemented as a C code library. This methodology could be used to provide support to other microcontroller families, such as PIC, STM and also more sophisticated controllers. These concepts are demonstrated through a few examples.

Fig: Workflow of NGHDL

Acknowledgment: The authors would like to thank Prof. Pramod Murali, Department of Electrical Engineering, IIT Bombay and Mrs. Usha Viswanathan, FOSSEE, IIT Bombay for their guidance. We would also like to express our gratitude towards Powai Labs Technology Private Limited for their gratis contribution to the VHPIDIRECT package and Utility package of NGHDL. The FOSSEE project is funded by the National Mission on Education through ICT, Ministry of Education, Govt. of India.

Special Issue on the 60th anniversary of the first laser

Special Issue on the 60th anniversary of the first laser Series I: Microcavity Photonics—from fundamentals to applications https://t.co/I9pRWzuxsQ #semi https://t.co/qW7HP2vfXd

— Wladek Grabinski (@wladek60) Jul 8, 2021

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from Twitter https://twitter.com/wladek60

July 08, 2021 at 03:39PM
via IFTTT

JFETLAB: simulate Si and 4H-SiC lDG JFET

JFETLAB, has been updated to v1.2, supporting DC/CV simulations of Si and 4H-SiC lDG JFET; the mobility and intrinsic concentration doping/temperature and temperature dependence are incorporate, respectively. Gm/Id simulations are also included. https://t.co/C7RK06oWhD #semi https://t.co/hiW6NswqPP

— Wladek Grabinski (@wladek60) Jul 8, 2021

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from Twitter https://twitter.com/wladek60

July 08, 2021 at 01:50PM
via IFTTT

[paper] Anti-ferroelectric/Ferroelectric Stack NC FinFET

Shih-En Huang¹, Student Member, IEEE, Pin Su¹, Member, IEEE, 

and Chenming Hu^1,2, Life Fellow, IEEE

S-curve Engineering for ON-state Performance 

using Anti-ferroelectric/Ferroelectric Stack Negative-Capacitance FinFET

2021 - techrxiv.org

1 Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University,  Hsinchu 30010, Taiwan  

2 Department of Electrical Engineering and Computer Science, University of California at Berkeley

Abstract: This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current (ION). The capacitance matching and ON-state performance are evaluated by using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current (IOFF) and ION relative to IRDS projections. There is significant long-term advantage to IC power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing.

Fig: (a) Equivalent capacitance network of the AFE/FE stack NC-FinFET. The Cafe, Cfe and Cint are the anti-ferroelectric capacitance, ferroelectric capacitance and the internal capacitance, respectively. (b) Capacitance matching comparison at source end shows that the AFE/FE stack improves the high AV region toward high VGS. 

Acknowledgment: The authors would like to thank anonymous referees for critical reading of the manuscript and valuable feedback. This work was supported in part by “Center for the Semiconductor Technology Research” from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE), Taiwan, and in part by the Ministry of Science and Technology, Taiwan, under contracts 110-2634-F-009-027 and 110-2218-E-A49-014-MBK.

[paper] A Compact Model of Gate Capacitance in Ballistic GAA-CNFET

A. Dixit, N. Gupta

A Compact Model of Gate Capacitance 

in Ballistic Gate-all-around Carbon Nanotube Field Effect Transistors 

IJE TRANSACTIONS A: Basics Vol. 34, No. 7, (July 2021) 1718-1724 

DOI: 10.5829/ije.2021.34.07a.16

* Nanomaterial Device Laboratory, Department of Electrical and Electronics Engineering,
Birla Institute of Technology and Science, Pilani, Rajasthan, India

Abstract: This paper presents a one-dimensional analytical model for calculating gate capacitance in Gate-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNFET) using electrostatic approach. The proposed model is inspired by the fact that quantum capacitance appears for the Carbon Nanotube (CNT) which has a low density of states. The gate capacitance is a series combination of dielectric capacitance and quantum capacitance. The model so obtained depends on the density of states (DOS), surface potential of CNT, gate voltage and diameter of CNT. The quantum capacitance obtained using developed analytical model is 2.84 pF/cm for (19, 0) CNT, which is very close to the reported value 2.54 pF/cm. While, the gate capacitance comes out to be 24.3×10-2 pF/cm. Further, the effects of dielectric thickness and diameter of CNT on the gate capacitance are also analyzed. It was found that as we reduce the thickness of dielectric layer, the gate capacitance increases very marginally, which provides better gate control upon the channel. The close match between the calculated and simulated results confirms the validity of the proposed model.

Fig. Schematic view of CNFET for modelling gate capacitance (a) front view (b) side view

Acknowledgements: Authors acknowledge the financial support of Defence Research and Development Organisation (DRDO), Govt. of India [ERIP/ER/DGMED&OS/990416502/ M/01/1657] and Nanomaterial device laboratory, BITS Pilani for carrying research out work reported this paper.