[paper] Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Ofogh Tizno, Andrew R. J. Marshall, Natalia Fernández-Delgado, Miriam Herrera, Sergio I. Molina
and Manus Hayne

Scientific Reports volume 9, Article number: 8950 (2019) 

DOI: 10.1038/s41598-019-45370-1

Abstract: Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10000s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.

FIG: Device structure a) Schematic of the processed device with control gate (CG), source (S) and drain (D) contacts (gold). The red spheres represent stored charge in the floating gate (FG). b) Cross-sectional scanning transmission electron microscopy image showing the high quality of the epitaxial material, the individual layers and their heterointerfaces.

Simulation Methods: The nextnano software package was utilised for mathematically modelling the energy band diagram of the memory device structure reported here, taking into account strain and piezoelectricity. Within this work, a self-consistent Schrödinger solver was used along with the Poisson and drift–diffusion equations to calculate the electron densities at equilibrium and under bias.

The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi https://t.co/TKw7mFqOcC

The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi pic.twitter.com/TKw7mFqOcC

— Wladek Grabinski (@wladek60) September 16, 2020

---

from Twitter https://twitter.com/wladek60

September 16, 2020 at 04:32PM
via IFTTT

FreePDK15: Process Design kit for 15-nm FinFETs

Development of a Predictive Process Design kit for 15-nm FinFETs: FreePDK15 

Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis 

arXiv:2009.04600v1 [cs.AR] 9 Sep 2020

Abstract: FinFETs are predicted to advance semiconductor scaling for sub-20nm devices. In order to support their introduction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer stack with thirteen-metal layers based on hierarchical-scaling used in ASIC architecture, Middle-of-Line local interconnect layers and a set of Front-End-of-Line layers. The physical and geometrical properties of these layers are defined and these properties determine the density and parasitics of the design. The design rules are laid down considering additional guidelines for process variability, challenges involved in FinFET fabrication and a unique set of design rules are developed for critical dimensions. Layout extraction including modified rules for determining the geometrical characteristics of FinFET layouts are implemented and discussed to obtain successful Layout Versus Schematic checks for a set of layouts. Moreover, additional parasitic components of a standard FinFET device are analyzed and the parasitic extraction of sample layouts is performed. These extraction results are then compared and assessed against the validation models.

FIG: Middle-of-Line layers used as interconnects

Acknowledgment: The authors would like to thank Paul Franzon at NC State University. The authors would like to thank Mentor Graphics, since this project would not have been possible without their generous gift of supporting funds and Calibre licenses. The authors would also like to thank Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend Wagieh and the team at Mentor Graphics for development of the first set of design rules and their constant support.In addition, the authors would like to thank and acknowledge Alexandre Toniolo at Nangate for clarifying the vision of MOL layers. We would also like to thank Cadence designsystems for use of the virtuoso software and Synopsys Inc.for use of Pycell studio. The authors would also like to thanks Vikas Sharma for P-Cells, Vidyanandgouda Patil for design rule fixes and Namrata Sampat for help cleaning up the distribution.

Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020)

Respected All

On behalf of the organizing committee of the Science Academies Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020),

I am sharing separate Zoom Links for each day. 

You are requested to register yourself for one or more sessions by registering separately.

Kindly forward this email to your friends, students and colleagues from all branches of science and engineering. 

• Kindly join at least 15 minutes before the session.
• Letter of attendance for each day will be provided at the end of the session.

September 15, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_JF5EVXqsTBCcHLIuL2e7dA)

• 04:00 pm – 05:00 pm - The Lead Halide Perovskites: Photoluminescence and Charge Carrier Dynamics - Professor Anunay  Samanta, FASc, FNASc, FNA, Sr. Professor and J.C. Bose National Fellow (DST), School of Chemistry, University of Hyderabad
• 05:00 pm – 06:00 pm  - Interdisciplinary Education for Science and Innovation - Professor Sourav Pal, FASc, FNASc, FNA, Director, Indian Institute of Science Education & Research, West Bengal  

September 16, 2020  (Zoom Link: https://zoom.us/webinar/register/WN_hbdn7CqUQMqWUeyaW7qJTA)

• 06:00 pm – 07:00 pm Electronic Cash, Cryptocurrencies and Smart Contracts - Professor Rudrapatna Kallikote Shyamasundar, FASc, FNA, FNASc, FNAE, FIEEE, FTWAS, Distinguished V Professor, Computer Science & Engineering Department, IIT Powai

September 17, 2020  (Zoom Link: https://zoom.us/webinar/register/WN_KG1XHg1gReWXDbW4Asg39w)

• 06:00 pm – 07:00 pm -  Indian Healthcare, Digital Transformation, and COVID-19 - Dr Anurag Agrawal, FNA, Director, CSIR-Institute of Genomics and Integrative Biology, Mall Road, Delhi University
• 07:00 pm – 08:00 pm  - Responsibilities and opportunities for academics in the context of current pandemic - Dr. Rakesh K Mishra, FASc, FNASc, FNA, Director, CSIR-Centre for Cellular & Molecular Biology, Hyderabad

September 18, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_Hqv3xXODT8-jkMuZmT3eXg)

• 06:00 pm – 07:00 pm - Continued fraction expansions of complex numbers - Prof. Shrikrishna Gopalrao Dani, FASc, FNA, FNASc, Distinguished Professor, Centre for Excellence in Basic Sciences, University of Mumbai, Maharashtra  
• 07:00 pm – 08:00 pm - C.R.Rao and Mahalanobis' Distance - Prof. Probal Chaudhuri, FASc, FNA, FNASc, Theoretical Statistics and Mathematics Unit, Indian Statistical Institute, Kolkata  
  

September 19, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_xDWQkmHdSl69mfci1yLnLA)

• 06:00 pm – 07:00 pm  - Future Geosciences and Opportunities - Prof. Ashok Kumar Singhvi, FASc, FNA, FNASc, FTWAS, Honorary Scientist, Atmospheric, Molecular & Optical Physics Divn., PRL, Gujarat
• 07:00 pm – 08:00 pm  - Glasses and other amorphous solids - Professor  Srikanth Sastry, FASc, FNASc, FNA, Theoretical Sciences Unit, JNCASR, Bangalore, Karnataka

with regards

Dr. Manoj Saxena | डॉ मनोज  सक्सेना 

Associate Professor | सह - आचार्य

Department of Electronics | इलेक्ट्रॉनिक्स विभाग

Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज

University of Delhi | दिल्ली विश्वविद्यालय

Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८

India | भारत

Official Homepage: https://dducollegedu.ac.in/ViewProfile.aspx?fId=saxenamanoj77@gmail.com

ORCID Webpage : http://orcid.org/0000-0002-9368-4194

Scopus Webpage : http://www.scopus.com/authid/detail.url?authorId=35480023200

ResearcherID-Thomson Reuters : http://www.researcherid.com/rid/K-3863-2015 

Publons Profile: https://publons.com/researcher/1341187/manoj-saxena

Please do not print this email unless it is absolutely necessary. Spread environmental awareness. 

[mos-ak] Fwd: ESSCIRC ESSDERC 2020 Virtual Educational Events | IMPORTANT MESSAGE

View this email in your browser ESSCIRC ESSDERC 2020 VIRTUAL EDUCATIONALS LIVE EXECUTIVE SESSIONS: September 14, 15  ON DEMAND September 7 - October 16 Hello, You are receiving this message because you registered for the ESSCIRC ESSDERC 2020 Virtual Educational Events. How is it going so far?  Feel free to use the Q&A box to send us questions: all questions will be gathered end of the week and will be transmitted to the event organizers prior to the Live events next week. Take also advantage of the POLLS in the following Educational Events:  3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems 10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data 11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities 12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization Questions and polls will be discussed during the LIVE EXECUTIVE SESSIONS. Mark your calendar! How to access the Live Executive Sessions? Once logged in, you see a small window on the left called "ADDITIONAL RESOURCES": the hyperlink to live session is there and, of course, it will be active only during live sessions  Last but not least, if you are experiencing some connections problems while using your office PC, check with your IT staff if firewalls prevent you from connecting to the on-line virtual events.  See you there! ORGANIZING COMMITTEE Thomas Ernst (CEA-LETI, FR), General co-chair Dominique Thomas (STMicroelectronics, FR), General co-chair François Andrieu (CEA-LETI, FR), ESSDERC TPC Chair Maud Vinet (CEA-LETI, FR), ESSDERC TPC co-Chair Andreia Cathelin (STMicrolectronics, FR), ESSCIRC TPC Chair Sylvain Clerc (STMicrolectronics, FR), ESSCIRC TPC co-Chair 2020 Virtual Educationals Chairs Sylvain Clerc (STMicrolectronics, FR) Ionut Radu (SOITEC, FR) LOCAL EXECUTIVE SECRETARIAT Sandra Barbier (CEA-LETI, FR) | sandra.barbier@cea.fr ORGANIZING SECRETARIAT Sistema Congressi s.r.l. | essxxrc@sistemacongressi.com  JOIN NOW OUR  ESSCIRC – ESSDERC LinkedIn group! Share Forward ORGANIZERS TECHNICAL SPONSORSHIP FINANCIAL SPONSORSHIP DIAMOND SPONSOR WATCH ME Copyright © 2020 Sistema Congressi s.r.l., All rights reserved. You are receiving this email because you registered for ESSCIRC ESSDERC 2020 Virtual Events Our mailing address is: Sistema Congressi s.r.l. Via Trieste 26 Padova, PD 35121 Italy Add us to your address book

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj_4EzeNd1cNwE-Jfx8nsGBrcSH3vN3KTxttAX2enMx96g%40mail.gmail.com.

2020 IEEE #IEDM To Highlight Innovative Devices for a #Better #Future

2020 IEEE #IEDM To Highlight Innovative Devices for a #Better #future https://t.co/8m1toPqhfI #paper pic.twitter.com/3FlTSlo3Id

— Wladek Grabinski (@wladek60) September 14, 2020

from Twitter https://twitter.com/wladek60

September 14, 2020 at 10:25AM
via IFTTT

[paper] Analogue 2D Semiconductor Electronics

Analogue two-dimensional semiconductor electronics

Dmitry K. Polyushkin¹, Stefan Wachter¹, Lukas Mennel¹, Matthias Paur¹, Maksym Paliy², Giuseppe Iannaccone², Gianluca Fiori², Daniel Neumaier^3,4, Barbara Canto^3,4

and Thomas Mueller¹ 

Nat Electron 3, 486–491 (2020)

DOI: 10.1038/s41928-020-0460-6

¹Vienna University of Technology, Institute of Photonics, Vienna, Austria. 
²Dipartimento di Ingegneria dell’Informazione, Università di Pisa, Pisa, Italy.
³AMO GmbH, Aachen, Germany. 

⁴Bergische Universität Wuppertal, Wuppertal, Germany

Abstract: Digital electronics are ubiquitous in the modern world, but analogue electronics also play a crucial role in many devices and applications. Analogue circuits are typically manufactured using silicon as the active material. However, the desire for improved performance, new devices and flexible integration has—as for their digital counterparts—led to research into alternative materials, including the use of two-dimensional (2D) materials. Here, we show that operational amplifiers—a basic building block of analogue electronics—can be created using the 2D semiconductor molybdenum disulfide (MoS2) as the active material. The device is capable of stable operation with good performance, and we demonstrate its use in feedback circuits including inverting amplifiers, integrators, log amplifiers and transimpedance amplifiers. We also show that our 2D platform can be used to monolithically integrate an analogue signal preconditioning circuit with a MoS2 photodetector.

Fig: a) Schematic of the back-gated transistor architecture; 

b) Transfer characteristics of a typical transistor on the chip (W/L = 4); 

c) View of a single OPA showing the pinout and transistor labelling

Circuit design and modelling: Because a complete model of back-gated 2D semiconductor FETs is still not readily available, we fitted the experimental results with an Enz–Krummenacher– Vittoz (EKV) model in both, the subthreshold and inversion, regimes. All the transistors operate in the inversion regime, we used the inversion model to simulate the OPA, obtaining a nominal low-frequency Atot gain value.

Acknowledgements: We thank A.J. Molina-Mendoza for technical assistance and N. Schaefer and J.A. Garrido for providing a polyimide substrate. We acknowledge financial support by the European Union (grant agreements 785219 Graphene Flagship, 796388 ECOMAT and 828901 ORIGENAL), the Austrian Science Fund FWF (START Y 539-N16) and the Italian MIUR (FIVE 2D).