Negative Capacitance Double-Gate JunctionlessFETs: A Charge-based Modeling Investigation of Swing, Overdrive and Short Channel Effect
Amin Rassekh, Jean-Michel Sallese, Farzan Jazaeri, Morteza Fathipour and Adrian M. Ionescu
IEEE TED, Vol. XX, No. XX, March 3, 2020
Abstract: In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectricon the I-V characteristics. Importantly, for the first time,our model predicts that the negative capacitance minimizes short channel effects and enhances current over-drive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels (0.1 μA/μm). Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.
Fig: The difference of the potential across the ferroelectric (left axis) and the difference of total charge density of ferroelectric (right axis) in high VDS and low VDS versus the channel length. ∆Vf somehow represents ∆VG (The difference of VG in high and low VDS). The inset illustrates the schematic of the I-V characteristic of a regular double gate JLFET and a double gate JLFET with negative capacitance at low and high VDS.
