Feb 22, 2016

Alliance: FOSS VLSI/CAD System



Alliance is a complete set of free cad tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at SoC department of LIP6 laboratory of the Pierre & Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

Alliance VLSI CAD System is free software. Binaries, source code and cells libraries are freely available under the GNU General Public License (GPL). You are welcome to use the software package even for commercial designs without any fee. You are kindly requested to mention: "Designed with Alliance © LIP6, Université Pierre et Marie Curie".

ICs Designed with Alliance
  • Smartlabs/Smarthome designed a complete circuit in the XFAB XH035 technology (2014).
  • Tokai University (Shimizu Lab) designed the SNX, a 16 bits processor in the ROHM 0.18µm (2010).
Useful Links

Feb 19, 2016

[video] How to Model RF Passive Devices: Spiral Inductors

How to Model RF Passive Devices: Spiral Inductors

With increasing operating frequencies, the modeling of passive components becomes increasingly important, and there exist no ready-to-use models for inductors, resistors, capacitors etc. Based on the other video of this fundamental device modeling series, (How to Model RF Capacitors and Resistors), this video extends the topic to modeling RF Spiral Inductors. It explains how to develop a Spice model based on verified S-Parameter measurements. Applying an easy to follow, step by step procedure, the video walks you through the entire modeling flow for on-wafer inductors, using the Keysight Measurement and Modeling Software IC-CAP.

The IC-CAP project (modeling spiral inductors with and without metal-1 shielding) can be downloaded together with a detailed pdf explaining the steps demonstrated in the video.

To download the project files referred to in this video visit:
http://www.keysight.com/find/eesof-how-to-model-spiral-inductors
Published on Feb 11, 2016

Feb 18, 2016

Feb 9, 2016

MIXDES 2016 Paper Submission Deadline

MIXDES Paper Submission Deadline
(March 1st, 2016)

---------- Forwarded message ----------
From: MIXDES 2016 Organizing Committee

Dear Colleagues,

I would like to kindly remind you that paper submission for MIXDES 2016 Conference has been already opened. The deadline for regular paper submission is March 1st, 2016, so I encourage you to register your papers. The instruction for paper preparation is available online. Please note that the paper format and content may be still updated up to Final Paper Version deadline (May 31st, 2016).

This year the MIXDES 2016 Conference will take place in Lodz, Poland, June 23-25, 2016. For more information regarding the conference please visit the MIXDES 2016 Conference web site at
www.mixdes.org.

If you have any questions please do not hesitate to contact me.

Hoping to see you in Lodz,

Mariusz Orlikowski
Secretary of the 23rd International Conference
"Mixed Design of Integrated Circuits and Systems"
MIXDES 2016
http://www.mixdes.org

Feb 7, 2016

Device to GDSII for IC Design Training

Hands on Training Program on “Device to GDSII for IC Design”
on 22-27 Feb 2016
Organized by VLSI Division of School of Electronics Engineering
Vellore Institute of Technology, Near Katpadi Rd Vellore, Tamil Nadu - 632014


The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap.

Target Audience: Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 40. 

Topics to ďe addressed:

Using TCAD:
  • Structure Creation, Simulation and Device Simulation 
  • Process Simulation 
  • Multi-gate Transistors 
  • Radiation study on devices and circuits
Using Cadence: 
  • RTL Design and Simulation 
  • Synthesis and low power synthesis Using RTL Compiler 
  • Physical aware synthesis and DFT 
  • Block and Top Level P&R Using SOC Encounter 
  • STA Using Timing Engine