This video explains and demonstrates a method to develop accurate SPICE models from verified S-parameter measurements. By using an easy to follow, step by step procedure, this video walks you through the entire modeling flow for an on-wafer capacitor, using the Keysight Measurement and Modeling Software IC-CAP.
The IC-CAP project can be downloaded, together with a detailed How-to-Use description, and an in-depth tutorial about passive components modeling, applying the demonstrated method.
[VIDEO]
Dec 16, 2015
Nov 18, 2015
[mos-ak] [Final Program] 8th International MOS-AK Workshop Washington DC December 9, 2015
8th International MOS-AK Workshop
Washington DC December 9, 2015
The Final MOS-AK Workshop Program
Washington DC December 9, 2015
The Final MOS-AK Workshop Program
Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Washington DC in the IEDM / CMC meetings timeframe on December 9, 2015. The MOS-AK workshop is organized with aims to strengthen an academic/industry network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Venue:
Embassy of Switzerland
2900 Cathedral Ave, NW,
Washington, DC 20008
USA
2900 Cathedral Ave, NW,
Washington, DC 20008
USA
Free Online Workshop Registration:
http://www.mos-ak.org/washington_dc_2015/registration.php
(any related inquiries can be sent to register@mos-ak.org)
(any related inquiries can be sent to register@mos-ak.org)
Workshop Agenda:
- MOS-AK Workshop - Dec, 9, 2015
- Online Technical Program http://www.mos-ak.org/
washington_dc_2015/ - 08:30 - 09:00 - On-site Registration
- 09:00 - 12:30 - Morning MOS-AK Session
- TCAD and Advanced CMOS Technologies
- Compact Modeling and Reliability Co-simulation
- 12:30 - 13:30 - Lunch
- 13:30 - 17:00 - Afternoon MOS-AK Session
- CMC Compact Model Standardization
- FOSS Tools for Compact Model Verilog-A Standardization
- 17:00 End of the workshop
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)
Extended MOS-AK Committee
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)
Extended MOS-AK Committee
WG/18/11/15
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Nov 11, 2015
[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient
[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015
Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6
URL / doi: 10.1109/ESSCIRC.2015.7313863
Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.
Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6
URL / doi: 10.1109/ESSCIRC.2015.7313863
Labels:
Analytical models,
BISM6,
ekv,
gm/ID,
IC,
Integrated circuits,
mosfet,
noise,
Radio frequency,
rf,
Silicon,
Transconductance,
Transistors
Location:
Graz, Austria
Oct 29, 2015
[Call for Participation] FOSDEM 2016 Electronic Design Automation Devroom
Call for Participation
FOSDEM 2016 Electronic Design Automation Devroom
This is the call for participation in the FOSDEM 2016 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Saturday 30 January 2016 in Brussels, Belgium. We are looking for contributions under the form of talks covering the following main topics:
- Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
- Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
- Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen)
- Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.
The submission process
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16
Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM16
before 4 December 2015.
If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "EDA devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.
Important dates
- 4 December 2015: deadline for submission of proposals
- 18 December 2015: announcement of final schedule
- 30 January 2016: devroom day
Labels:
CAD,
compact modeling,
EDA,
FOSDEM,
FOSS,
GnuCap,
ngspice,
open source,
PCB,
QUCS,
spice,
TCAD,
Verilog-A standardization,
Xyce
Location:
Brussels, Belgium
Oct 23, 2015
[Purdue e-Pubs] A physics-based compact model for thermoelectric devices
A physics-based compact model for thermoelectric devices
Kyle Conrad, Purdue University; Mark S. Lundstrom, Purdue University (Advisor)
Abstract: Thermoelectric devices have a wide variety of potential applications including as coolers, temperature regulators, power generators, and energy harvesters. During the past decade or so, new thermoelectric materials have been an active area of research. As a result, several new high figure of merit (zT) materials have been identified, but practical devices using these new materials have not yet been reported. A physics-based compact model could be used to simulate a thermoelectric devices within a full system using SPICE-compatible circuit simulators. If such a model accepts measured or simulated material parameters, it would be useful in exploring the system level applications of new materials. In this thesis, the ground work for such a compact model is developed and tested. I begin with a discussion of thermoelectric transport theory within the Landauer formalism. The Landauer formalism is used as the basis of the tool LanTraP, which uses full band descriptions to calculate the distribution of modes and thermoelectric transport parameters, which can serve as the input to a compact model. Next, an equivalent circuit model is presented, explained, and tested using a simple Bi2Te 3 thermoelectric leg. The equivalent circuit is shown to perform well under a variety of DC, transient, and AC small signal operating conditions. With the equivalent circuit it is easy to determine the maximum cold side temperature drop, the maximum cold side heat absorbed, the temperature profile within the leg, the temperature response to a pulsed current, and impedance over a range of frequencies. Finally, Sentaurus®, a computer program that solves the thermoelectric transport equations numerically, is used to compare and benchmark some of the results of the equivalent circuit when considering Si as the thermoelectric material. The equivalent circuit and Sentaurus® simulations produce similar results in DC and transient cases, but in the AC small signal case the two simulations produce slight differences. The results of this work establishes a baseline compact model for thermoelectric devices whose accuracy and capabilities can be extended.
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