CTFT 2012

4th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation

This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with Cambridge University. A partial list of the areas of interest includes:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The workshop organizers:
Department of Engineering, University of Cambridge, Cambridge, UK
Technical School of Engineering, University Rovira i Virgili, Tarragona, Spain

[mos-ak] Final Program: 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the technical program sponsor, as well as with the industrial sponsors Agilent Technologies, LFoundry, CSEM, STM, AMS we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The final workshop program is available on-line: <http://mos-ak.org/bordeaux/> 

To register please visit official ESSDERC/ESSCIRC registration website.

- with regards - WG (for the MOS-AK/GSA Committee) 

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MOS-AK/GSA Bordeaux (F) Sept.21, 2012 

MOS-AK/GSA San Francisco, CA Q4 2012 

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Why- and how- to integrate Verilog-A compact models in SPICE simulators

A nice paper from Maria-Anna Chalkiadaki, Cédric Valla, Frédéric Poullet, and Matthias Bucher:

Why- and how- to integrate Verilog-A compact models in SPICE simulators

This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.

Birthday (61) of the JUNCTION transistor

From EDN:

Bell Labs and primarily William Shockley announced the invention of the junction transistor at a press conference in Murray Hill, NJ, the first week of July, 1951.
Sources vary as to when the formal announcement was actually made, July 4, 1951, or July 5, 1951.
At the time, Shockley was with Bell Labs’ solid state physics group, a unit to which he was a group head and a unit that saw much internal competition.
This new type of transistor overcame problems created by earlier point-contact transistors, developed by Bell Labs’ Joe Bardeen and Walter Brattain without Shockley but based in part on his previous work. It is said that when the patent process began for the point-contact transistor, Shockley made an effort to have his name only placed on the patent and made sure his fellow engineers knew of that effort.
Shockley has been described as having a “tremendous ego” by his co-workers. He was also known as having openly racist views.
Although Shockley is often known as “the inventor” of the transistor and despite his reported ego, he was often noted as correcting such misstatement and noting that he led the effort with others involved. Notes made during the development of the junction transistor can be viewed here.
Shockley left Bell Labs a few years after working on the junction transistor and eventually became a professor emeritus of electrical engineering at Stanford. He died on campus in 1989 at the age of 79.

For more moments in tech history, see this blog.

NANOTEC-Tutorial at ESSCIRC/ESSDERC in Bordeaux on 09/17/2012

The NANO-TEC project will held a half day tutorial at the ESSDERC/ESSCIRC Conference in Bordeaux on Monday, September 17, 2012. This Tutorial will be on the ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS in Europe and will present the current outcome of the EU project NANOTEC [read more...]