Sep 29, 2026

[paper] TCAD Modeling of SB Diode

Pedro Paulo Pessoa Oliveira1,2, Andreas Mai1,3, Norbert Herfurth1, 
and Davies William de Lima Monteiro2
TCAD Modeling of Schottky-Diode in an open-source SiGe BiCMOS technology
In 2026 40th Symposium on Microelectronics Technology and Devices 
SBMicro, pp. 1-4. IEEE, 2026
DOI: 10.1109/SBMicro70495.2026.11684441

1. IHP, Frankfurt (Oder), Germany
2. Department of Electrical Engineering, UFMG - Belo Horizonte-MG, Brazil
3. University of Applied Sciences Wildau, Germany

Abstract: Accurate simulation of Schottky barrier diodes (SBDs) is challenging because standard idealized models fail to capture non-ideal interface physics, such as Fermi-level pinning and image-force lowering. This paper presents an enhanced Technology Computer-Aided Design (TCAD) methodology to model an SBD from the IHP SG13G2 130-nm open-source SiGe BiCMOS technology. To overcome limitations of conventional simulations that often rely on oversimplified assumptions and empirical fitting, this work explicitly incorporates interface en- ergy states into the simulation, specifically modeling the fun- damental pinning mechanisms driven by Metal-Induced Gap States (MIGS). By calibrating the TiSi2/Si interface using the theoretical slope parameter, a value of 0.503 V was determined for the zero-bias barrier height. The resulting physics-based model captures the true rectifying nature of the contact and accurately reproduces the electrical characteristics targeted by the empirical model, achieving a nominal forward voltage drop of 0.39 V and a realistic reverse leakage current of 29.3 nA at -2.5 V. Ultimately, this paper shows the innovation and education gain of open- source foundry data by showcasing an open innovation path for a targeted near-industry device development flow.
FIG: a.) Energy band diagram of the Schottky diode at V=0V. Thecoordinate x = 0 corresponds to the TiSi2/n-Si Schottky interface. The inset displays the 2D device schematic, with the solid black line indicating the multi-segment cut-path used to extract the energy levels across the anode, n-buried layer and n-well RT to cathode contact. b.) Comparison of the simulated DC current-voltage (IV) characteristics between the proposed TCAD model and the standard SPICE macromodel.

Acknowledgment: The authors thank IHP for the open-source PDK and the collaborative research. They also thank Universidade Federal de Minas Gerais (UFMG) and the Brazilian Microelectronics Society (SBMicro) for supporting this work. Finally, gratitude is extended to S. Srivastava and B. Sake for their valuable guidance.

Sep 28, 2026

[NanoIC] Workshop

NanoIC Pilot Line Workshop
Next logic, memory, and chiplet technologies to enable future system innovation
October 1, 2026; Sede Turismo Andaluz; 40 Compañía Str. Málaga, Spain

Workshop Agenda

10:00 - 10:10 Welcome
10:10 - 10:30 Marie Garcia Bardon 
Short Introduction to EU Chips Act NanoIC Pilot Line
10:30 - 11:30 Nicolas Pantano 
Enabling Chiplet Architectures Through Advanced Packaging And High-Density Interconnects
11:30 - 12:00 Coffee break
12:00 - 13:00 Fernando García Redondo 
Opportunities in memory scaling: design-technology co-optimization for SRAM and emerging memories
13:00 - 14:00 Marie Garcia Bardon 
Advanced Logic Scaling: Technologies for the sub-2nm

Free Registration Online Workshop  
               https://u.uma.es/icc/workshop

Sep 26, 2026

[ChipFoundry] December Shuttle: Commitment deadline moved to November 4th

Sep 25, 2026

[paper] EKV compact modeling for oxide CTFTs

Mingyu Zhuang, Zhiyuan Wang, Baochuan Liu, Jiawei Zhang, Qian Xin, Aimin Song
Neural-network-assisted EKV compact modeling for complementary oxide thin-film transistors
Appl. Phys. Lett. 129, 123504 (2026)
DOI: 10.1063/5.0349365

1. Shandong Technology Center of Nanodevices and Integration, Uni. Shandong (CN)
2. Department of Electrical and Electronic Engineering, Uni. Manchester (UK)
3. Southern University of Science and Technology, Shenzhen (CN)

ABSTRACT: This work reports a neural-network-assisted Enz–Krummenacher–Vittoz (EKV) compact-modeling framework for complementary oxidethin-film transistors (TFTs). The neural network is used as a bias-dependent effective-parameter generator for the equivalent mobility and onset voltage, while the drain current is calculated by the analytical EKV current core. This strategy represents defect-, contact-, and bias-dependent nonidealities of oxide TFTs through effective quantities without replacing the current equation with a black-box neural-networkpredictor. The model is validated using both n-type indium–gallium–zinc oxide TFTs and p-type tin monoxide (SnO) TFTs, achieving mean absolute percentage errors of 0.56% and 0.36%, respectively. The learned effective parameters further provide an EKV-constrained compact representation of bias-dependent transport capability and channel-onset behavior obtained from global fitting of the measuredoutput-characteristic dataset, rather than serving as directly extracted material parameters. The trained model is translated into aPSpice-compatible library and applied to complementary inverter simulation, showing good agreement with measured voltage-transfer characteristics and reproducing the main transient response characteristics. These results demonstrate an accurate, analytically structured, and Simulation Program with Integrated Circuit Emphasis-compatible compact-modeling strategy that links bias-dependent oxide-TFTtransport to circuit-level simulation. 

FIG. (a) Equivalent parasitic‑capacitance and measurement‑loading network used in the transient simulation of the complementary SnO/IGZO inverter. (b) Simulated output waveforms for different values of the additional external capacitance.

Selected References:
[24] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. 8, 83–114 (1995)
DOI: 10.1007/BF01239381
[25] J.-M. Sallese et al, “Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model,” Solid-State Electron. 47, 677–683 (2003) 
DOI: 10.1016/S0038-1101(02)00336-2
[26] W. Grabinski et al, “FOSS EKV 2.6 parameter extractor,” in Proceedings of the 22nd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES) (IEEE, 2015), pp. 181–186
DOI: 10.1109/MIXDES.2015.7208507

Sep 23, 2026

[100FET] IEEE EDS Egypt Chapter

IEEE EDS Egypt Chapter - 100 Years FET

Theme: Overview and celebration of 100 years of FET research
Location: Zewail City of Science and Technology Campus; October Gardens; 6 of October City
Date: Sept. 27-28, 2026

Main Objectives:
This event celebrates the 100th anniversary of the Field-Effect Transistor (FET) by highlighting its evolution over the past century and exploring future trends in electron devices. It also promotes the activities and membership of the IEEE EDS Egypt Chapter. The event aims to:
  • Technical Advancement: Discuss recent developments in FET fabrication, modeling, simulation, and operation
  • Knowledge Exchange: Share insights on the historical evolution and future directions of FET technologies
  • Professional Networking: Foster collaboration among students, researchers, academics, and industry professionals
  • Skill Development: Provide hands-on TCAD workshops to enhance practical device simulation skills
  • Membership Growth: Increase the visibility of the IEEE EDS Egypt Chapter and encourage new memberships
Agenda
Time Activity Description
  Day 1 Sunday, 27th of September 2026
08:30 – 09:30 Registration Welcoming participants and distribution of materials
09:30 – 10:00 Welcome Speech Welcome speeches by the faculty leaders
10:00 – 11:00 Distinguished Lecturer #1
Dr. Hisham Omran
Focus on FET evolution
11:00 – 12:00 Networking Break Refreshments & snacks
12:00 – 13:00 Distinguished Professor #2 Focus on FET research trends
13:00 – 14:00 Women in Engineering Talk
Dr. Shereen Youssef
Talk by IEEE WIE Egypt Chair
14:00 – 15:00 Q&A Interactive Discussion Interactive discussion:
- Academia vs. Industry in FETs
  Day 2  Monday, 28th of September 2026
08:30 – 09:00 Registration Welcoming participants and distribution of materials
09:00 – 11:00 Workshop #1:
TCAD Modelling of FET Devices
Eng. Amr W. Shalaby
TCAD workshop #1:
- Introduction to the TCAD tool
- Simulation of a MOSFET
- Doping electrical characterization
11:00 – 12:00 Networking Break Refreshments
12:00 – 13:00 Workshop #2
Eng. Yasmine AbdulAal
Senior design engineer at Siemens
TCAD workshop #2
- Compact modelling for next-gen electronics 
13:00 – 13:30 Panel / Q&A TCAD in academia and industry
13:30 – 14:30 Closing Ceremony Certificates and giveaways