[Conference] 33rd Austrochip 2025

Austrochip 2025

33rd Austrian Workshop on Microelectronics

September 25, 2025 – Linz, Austria

The TT workshop program

Conference Program

08:00 – 09:00 Coffee & Registration
09:00 – 09:15 Conference Opening
09:15 – 10:00 First Keynote-Address

• IHP OpenPDK and MPW: Pushing Open-Source EDA tools to Analog and RF Design René Scholz IHP – Leibniz Institute for high performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

10:00 – 10:45 Second Keynote-Address

• Open-source SoC design using PULP Frank K. Gürkaynak ETH Zürich, IIS, ETZ J 60.1, Gloriastrasse 35, 8092 Zürich, Switzerland

10:45 – 11:00 Break
11:00 – 12:00 Paper Session I:
Session Chair: TBA, TBA

• Gain Expansion Generator based on a Reduced Conduction Angle for H-Band Applications Thomas Ufschlag, Benjamin Schoch, Lukas Gebert, Dominik Wrana, Axel Tessmann and Ingmar Kallfass University of Stuttgart (ILH), Fraunhofer Institute for Applied Solid State Physics IAF
• Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2 Leo Moser, Meinhard Kissich, Tobias Scheipel and Marcel Baunach Graz University of Technology
• Comparison of Low Power Digitally Controlled Ring Oscillator Architectures in 12 nm FinFET Florian Schneider, Luca Avallone and Alicja Michalowska-Forsyth Infineon Technologies Austria AG Institute of Electronics (IFE), Graz University of Technology

12:00 – 12:30 Poster & Sponsor Pitch Session
12:30 – 14:00 Lunch
14:00 – 15:15 Paper Session II:
Session Chair: TBA, TBA

• A 150-GHz 9-dBm EIRP Open-Source FMCW Radar Chip in 130-nm BiCMOS Ghaith Al Sabagh, Georg Zachl and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz

• A CMOS Source-Coupled Relaxation Oscillator Achieving Close-in Phase Noise of −72.9 dBc/Hz at a 1 kHz Offset Baset Mesgari, Saeed Saeedi, Reinhard Feger and Horst Zimmermann Institute for Communications Engineering and RF-Systems, Johannes Kepler University Linz Faculty of Electrical and Computer Engineering, Tarbiat Modares University Christian Doppler Laboratory MWTH

• A FR3, 25 dBm Unbalanced MMIC GaAs Doherty Power Amplifier with Auxiliary Gate Voltage Modulation for Linearity Improvement Abdolhamid Noori, Fatemeh Abbassi, Christoph Wagner, Christian Fager and Gregor Lasser Chalmers University of Technology, Silicon Austria Labs

• A 72.7-90.4 GHz VCO with a Stacked NMOS based Tuning Network in 28nm FDSOI Waseem Abbas, Samir Aziri and Christoph Wagner Silicon Austria Labs

• A D-Band Active Down-Conversion Mixer with 80 GHz IF for FMCW Radar Frequency Extension Fatemeh Abbassi, Samir Aziri, Waseem Abbas, Christoph Wagner and Timm Ostermann Silicon Austria Labs, Institute for Integrated Circuits and Quantum Computing, JKU Linz

15:15 – 15:30 Break
15:30 – 16:45 Paper Session III:
Session Chair: TBA, TBA

• Design Automation of a Digitally Controlled Ring Oscillator using CUAS Cell Creator Framework Daniel Cerdà Holmager, Santiago Martin Sondón, Violeta Petrescu, Wolfgang Scherr and Johannes Sturm Carinthia University of Applied Sciences in Austria, CUAS
• Event-Based ADCs vs. Nyquist ADCs: Rethinking Performance Metrics Simon Dorrer, Anna Werzi, Bernhard A. Moser, Michael Lunglmayr and Harald Pretl Institute for Integrated Circuits and Quantum Computing, JKU Linz Institute of Signal Processing, JKU Linz
• Modeling Location-dependent Random Telegraph Noise for Circuit Simulators Florian Berger, Gerhard Landauer, Alicja Michalowska-Forsyth, Martin Flatscher, Philipp Greiner and Stefan Gansinger Institute for Electronics, Graz University of Technology Power and Sensor Systems, Infineon Technologies
• An 8.1-µW 12-bit Non-Binary Self-Clocked SAR-ADC in 130 nm Open-Source PDK Ali Olyanasab, Patrick Fath, Leonhard Schreiner, Christoph Guger and Harald Pretl g.tec medical engineering GmbH Institute for Integrated Circuits and Quantum Computing, JKU Linz
• SPAD Active Quenching/Resetting Circuit in 0.35-µm HV-CMOS Enabling 24V Excess Bias for PDP >90% Sherwin Nasirifar, Baset Mesgari, Christoph Ribisch, Saman Kohneh Poushi and Horst Zimmermann Institute of Electrodynamics, Microwave and Circuit Engineering, TU Wien Institute for Communications Engineering and RF Systems, JKU Linz Austrian Institute of Technology (AIT), Vienna Silicon Austria Labs

16:45 – 17:00 Conference Closing, Best Paper Award & Outlook Austrochip 2026

Aging Model for ASAP 7nm Predictive PDK

Neha Gupta¹, Lomash Chandra Acharya¹, Mahipal Dargupally¹, Khoirom Johnson Singh², Amit Kumar Behera¹, Johan Euphrosine³, Sudeb Dasgupta¹, Anand Bulusu¹

Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System

IEEE ISVLSI (2025)

DOI: 10.1109/ISVLSI65124.2025.11130265

1 Indian Institute of Technology, Roorkee, (IN)
2 Dhanamanjuri University, Manipur (IN)
3 Google, Tokyo (J)

Abstract: As semiconductor technology advances to sub- 10nm nodes, Design Technology Co-Optimization (DTCO) has emerged as an essential paradigm for co-optimizing processes and design methodologies. Although the ASAP 7nm Predictive PDK (Process Design Kit), which is a free and open-source academic PDK developed by the Arizona State University (ASU) research team, is a useful open-source platform for digital design research, it lacks key DTCO features such as reliability modeling, aging resilience, and security-aware co-design. In this article, we present our developed aging model for ASAP 7nm Predictive PDK and utilize it to evaluate the impact of transistor aging on the performance of digital timing logic and a memory cell which provides timing feedback from a DTCO point-of-view concerning standard cells and other reference circuit designing. In this work, different logic gates, benchmark circuits, N-stage ring oscillator and 6T SRAM bitcell are used as the representative of digital logic and memory cell, respectively. We further utilize our developed aging model to predict performance of an analog-to-digital converter in data acquisition systems. The developed aging model would be released for the research community for further improvement in design reliability and technology enhancement along with OPENROAD Tool flow.

Fig. (a) Flow chart for representing steps required to develop Verilog-A aging model 

for ASAP 7nm Predictive PDK (FinFET) process. 

(b) Inclusion of the developed aging model to incorporate aging impact in static timing analysis (STA).

FOSSEE eSim Marathon – Circuit Design & Simulation with IHP SG13G2

Design, Simulate, Showcase

Unlock Open-Source VLSI Design  using eSim + IHP SG13G2 OpenPDK!!!

The eSim Marathon - Circuit Design & Simulation with IHP SG13G2 is a nationwide circuit design competition where participants use eSim, an open-source EDA tool developed by FOSSEE, IIT Bombay, to design and simulate circuits using the IHP OpenPDK for 130nm SG13G2 BiCMOS technology from IHP Microelectronics, Germany.

Key Highlights:

• Tool Used: eSim - a free and open-source alternative to commercial circuit design tools 
• OpenPDK Used: IHP SG13G2 - enables design of analog, digital, and RF circuits at 130 nm BiCMOS.
• Objective: Design, simulate, and submit functional analog/digital/mixed-signal circuits.
• Eligibility: Open to individuals - students, hobbyists, and early-career professionals.
• Learning Outcomes: Participants gain hands-on VLSI design experience using a real foundry OpenPDK, develop schematics, run simulations, and build documentation - entirely with open tools.

Register < https://esim-marathon.netlify.app/register/ >

Timeline

Date	Activity	Description
1 Sept. - 15 Sept. 2025	Registration for the Marathon	Complete the participation form
16 Sept. 2025	Marathon Inauguration Webinar	FOSSEE Team will introduce through eSim, IHP and Marathon process
16 Sept. - 23 Sept. 2025	Literature Survey	Participants need to research the topic available in papers/journals on the web
23 Sept. 2025	Report Submission	Submit one-page research conclusion and circuit implementation plan
23 Sept. - 5 Oct. 2025	Implementation	Design, characterise and simulate using eSim platform
5 Oct. - 8 Oct. 2025	Report Submission & Documentation	Upload reference and actual circuit/waveform using eSim
25 Oct. 2025	Result Declaration (Provisional)	Announcement of provisional results

[paper] Human Language to Analog Layout

Ali Hammoud, Chetanya Goyal, Sakib Pathen, Arlene Dai, Anhang Li, Gregory Kielian,
and Mehdi Saligane

Human Language to Analog Layout Using GLayout Layout Automation Framework

ACM/IEEE MLCAD 

https://doi.org/10.1145/3670474.3685971

Abstract: Current approaches to Analog Layout Automation apply ML techniques such as Graph Convolutional Neural Networks (GCN) to translate netlist to layout. While these ML approaches have proven to be effective, they lack the powerful reasoning capabilities, an intuitive human interface, and standard evaluation benchmarks that have been improving at a rapid development pace in Large Language Models (LLMs). The GLayout framework introduced in this work translates analog layout into an expressive, technology generic, compact text representation. Then, an LLM is taught to understand analog layout through fine-tuning and in-context learning using Retrieval Augmented Generation (RAG). The LLM is able to successfully layout unseen circuits based on new information provided in-context. We train 3.8, 7, and 22 Billion parameter quantized LLMs on a dataset of less than 50 unique circuits, and text documents providing layout knowledge. The 22B parameter model is tuned in 2 hours on a single NVIDIA A100 GPU. The open-source evaluation set is proposed as an automation benchmark for LLM layout automation tasks, and ranges from 2-transistor circuits to aΔΣ ADC. The 22B model completes 70% of the tasks in the evaluation set, and passes DRC and LVS verification on 44% of evaluations with verified correct blocks up to 4 transistors in size.

FIG: Full process of translating user prompt to a final layout.

Acknowledgments: The authors would like to thank the open-source community for their support.

 

[paper] Differential Aging-Aware Static Timing Analysis

Lomash Chandra Acharya, Neha Gupta, Khoirom Johnson Singh, Mahipal Dargupally, Neeraj Mishra, 

Arvind Kumar Sharma, Ajoy Mondal, Venkatraman Ramakrishnan, 

Sudeb Dasgupta, and Anand Bulusu

DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin

in IEEE Transactions on Device and Materials Reliability

DOI: 10.1109/TDMR.2025.3603098

1.) Department of Electronics and Communication Engineering, IIT Roorkee (IN)
2.) Department of Electronics, Dhanamanjuri University, Imphal (IN)
3.) Department of Electronics and Electrical Engineering, BITS Pilani (IN)
4.) Semiconductor Technology and Systems Department, IMEC (B)
5.) EDA Group, Texas Instruments, Bengaluru (IN)
6.) OnSemi Technology, Bengaluru (IN)

Abstract : This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.

FIG: Representation of the approach used to model a standard cell 

with transistor topology of a buffer and its terminal transitions as a test case.