SSCS PICO Chronicle

Mirjana Videnovic-Misic, Harald Pretl, Ali Sabir, Zonghao (Chris) Li, 

and Sadayuki Yoshitomi

SSCS PICO Chronicles: news from the open source community

Date of current version: 14 November 2023

DOI: 10.1109/MSSC.2023.3315888

The Growing Activity of Open Source Chip Design in Japan

The Chipathon 2023 Team Japan consists of 12 volunteers from industry and academia. Since the team members are located in different parts of Japan, the team will be working remotely to design the project. On 4 August, they held a kickoff meeting where the members, who had been working together on Slack, gathered for the first time in person. Although many of the team members have no tape-out experience, they are all truly interested in IC design. The leader of Team Japan is Prof. Akira Tsuchiya at the University of Shiga in Japan (FIG).

Prof. Tsuchiya has been working on open source IC design and has been a volunteer member of the SSCS Chipathon since October 2022. He has promoted open source IC design and SSCS PICO activities in Japan. He held several hands-on events, for example, at the summer camp of the IE- ICE ICD in 2022. Also, he gave several talks about open source IC design and his research on analog synthesis in domestic conferences. And now, he has recruited members and applied to the latest Chipathon. Let’s look forward to the activities of the new members of “Team Japan.”

FIG: Prof. Akira Tsuchiya, an associate professor of the University of Shiga prefecture, 

Japan, and a snapshot of the kickoff meeting (hybrid) of the Chipathon 2023 Japan team

[C4P] MIEL 2025

34th IEEE International Conference on Microelectronics 

(MIEL 2025) 

Niš, Serbia, Oct. 13-16, 2025

Organized by

Faculty of Electronic Engineering, Uni. Nis

IEEE Serbia and Montenegro Section - ED/SSC Chapter

in cooperation with Serbian Academy of Sciences and Arts - Branch in Nis

under the co-sponsorship IEEE Electron Devices Society

under the auspices of

Serbian Ministry of Science, Technological Development 

and Innovation Society for ETRAN

Abstracts Submission

The authors of contributed papers are expected to submit two-page extended abstracts (including figures, tables, and references) that will serve for the paper selection. A cover page of the abstract should include the paper title, authors, and complete address (including fax and e-mail) of the author to be contacted. The abstracts can be submitted in electronic form (either MS Word, PDF, or PostScript files) via E-mail sent to Conference Secretariat (miel@elfak.ni.ac.rs) by April 25th, 2025. Also, the abstracts can be submitted via System for manuscript submission.

Review Process

Only abstracts that have not been previously published at the time of the conference will be considered. Peer review refers to the evaluation and assessment of submitted two-page extended abstracts by experts in the field of microelectronic devices, circuits, and systems. Note that the most frequent cause of rejection of submitted two-page extended abstracts is lack of new results.

Important Dates

• December 31, 2024 First Announcement and Call for Papers
• April 25, 2025 Deadline for Receipt of Abstracts
• June 20, 2025 Notification on Acceptance of Papers
• September 01, 2025 Deadline for registration
• September 05, 2025 Deadline for Receipt of Papers
• September 29, 2025 Dispatch of Conference Programme

Note for Authors
Extended versions of selected papers from MIEL 2025 Conference will be published (after the regular review process) in:

• Journal of Circuits, Systems and Computers
• Facta Universitatis, Series: Electronics and Energetics
• Electronics, MDPI

Programme Committee Chairman

Danijel Danković; Faculty of Electronic Engineering, University of Niš

Vojkan Davidović; Faculty of Electronic Engineering, University of Niš

Contact details:

Faculty of Electronic Engineering, Uni. Nis

Aleksandra Medvedeva 14, 18000 Nis, Serbia

phone: +381 18 529 325, +381 18 529 326

fax: +381 18 588 399

E-mail: miel@elfak.ni.ac.rs

[C4P] ICMC 2025

STRENGTHENING MODELING COLLABORATION WITH THE SEMICONDUCTOR INDUSTRY

International Compact Modeling Conference (ICMC 2025)

June 26-27, 2025; The Clift Royal Sonesta, San Francisco

IMPORTANT DATES Abstract Submission Deadline January 15, 2025 Acceptance Notifications March 10, 2025 Full Paper Submission Deadline April 20, 2025 ORGANIZING COMMITTEE General Chair Peter M. Lee Micron  Vice Chair Shahed Reza Sandia Lab Technical Program Chair Colin Shaw Silvaco Technical Program Vice Chair Gert-Jan Smit NXP  Treasurer Leigh Anne Clevenger Si2 Secretariat Conference Catalysts icmc@conferencecatalysts.com

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For 30 years now, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing a new and innovative International Compact Modeling Conference. Cosponsored by IEEE EDS, it will focus uniquely on compact device models, their development and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guide model development to help circuit designers create the best circuit performance possible, and enable foundries to leverage the strength of their device fabrication to full extent. Join the world experts in design, process technology, and model development to discuss state-of-the-art semiconductor device modeling for a two-day in-person event in one location, offering a great opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations. We are seeking papers for oral or poster presentations in the following areas: APPLICATION OF DEVICE MODELS Innovative application of CMC standard device models Best practices, novel use, and benefits of standard device models in circuit design Use of compact models to demonstrate foundry device capabilities DEVICE MODEL DEVELOPMENT Modeling of physical phenomena: Statistical variation, reliability and aging, noise and fluctuations, high frequency effects, Electrostatic Discharge (ESD), self heating, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies, including solutions based on AI or Machine Learning. MODEL ENHANCEMENTS AND IMPLEMENTATIONS Model extensions to capture additional device features (leakage, noise, capacitance, second-order dependencies, …) or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. MODELING FOR FUTURE/EMERGING TECHNOLOGIES AND APPLICATIONS Models for emerging device types or architectures on the horizon, such as, ferroelectric devices, silicon photonics, cryogenic, quantum computing, etc. Modeling of new physical phenomena in support of current and novel device technologies Novel device technologies currently being researched that could further revolutionize circuit performance, have implications in the design flow, and may become mainstream in the future Please submit your paper proposals in the form of a 2-page abstract for review by January 15, 2025 here 2025.si2-icmc.org. Acceptance notifications will be sent by March 10, 2025. Accepted contributions (for both oral and poster presentations) are expected to submit a camera-ready 4-page draft version of their papers by April 20, 2025 and final version by May 23, 2025 for publication in IEEE Xplore®.

[C4P] International Compact Modeling Conference

STRENGTHENING MODELING COLLABORATION WITH THE SEMICONDUCTOR INDUSTRY

International Compact Modeling Conference (ICMC 2025)

June 26-27, 2025; The Clift Royal Sonesta, San Francisco

IMPORTANT DATES Abstract Submission Deadline January 15, 2025 Acceptance Notifications March 10, 2025 Full Paper Submission Deadline April 20, 2025 ORGANIZING COMMITTEE General Chair Peter M. Lee Micron  Vice Chair Shahed Reza Sandia Lab Technical Program Chair Colin Shaw Silvaco Technical Program Vice Chair Gert-Jan Smit NXP  Treasurer Leigh Anne Clevenger Si2 Secretariat Conference Catalysts icmc@conferencecatalysts.com

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For 30 years now, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing a new and innovative International Compact Modeling Conference. Cosponsored by IEEE EDS, it will focus uniquely on compact device models, their development and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guide model development to help circuit designers create the best circuit performance possible, and enable foundries to leverage the strength of their device fabrication to full extent. Join the world experts in design, process technology, and model development to discuss state-of-the-art semiconductor device modeling for a two-day in-person event in one location, offering a great opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations. We are seeking papers for oral or poster presentations in the following areas: APPLICATION OF DEVICE MODELS Innovative application of CMC standard device models Best practices, novel use, and benefits of standard device models in circuit design Use of compact models to demonstrate foundry device capabilities DEVICE MODEL DEVELOPMENT Modeling of physical phenomena: Statistical variation, reliability and aging, noise and fluctuations, high frequency effects, Electrostatic Discharge (ESD), self heating, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies, including solutions based on AI or Machine Learning. MODEL ENHANCEMENTS AND IMPLEMENTATIONS Model extensions to capture additional device features (leakage, noise, capacitance, second-order dependencies, …) or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. MODELING FOR FUTURE/EMERGING TECHNOLOGIES AND APPLICATIONS Models for emerging device types or architectures on the horizon, such as, ferroelectric devices, silicon photonics, cryogenic, quantum computing, etc. Modeling of new physical phenomena in support of current and novel device technologies Novel device technologies currently being researched that could further revolutionize circuit performance, have implications in the design flow, and may become mainstream in the future Please submit your paper proposals in the form of a 2-page abstract for review by January 15, 2025 here 2025.si2-icmc.org. Acceptance notifications will be sent by March 10, 2025. Accepted contributions (for both oral and poster presentations) are expected to submit a camera-ready 4-page draft version of their papers by April 20, 2025 and final version by May 23, 2025 for publication in IEEE Xplore®.

[job opening] Assembling Design Kit (ADK) Developer

IHP's growing Open Source PDK group is seeking a new team member!

The open-source initiative is evolving rapidly with many plans for the future, and this role is critical for driving the development of an Assembling Design Kit (ADK) for hetero and chiplet integration projects.

As part of the Research & Prototyping Service group, you will develop open-source EDA tool support, evaluate design tools for ASICs on a common substrate, implement and document the ADK, and focus on mixed-signal and RF applications up to 100 GHz, utilizing both open-source and proprietary tools.

The ideal candidate holds a Master’s degree in Computer Science with a background in semiconductors, physics, or electrical engineering. Expertise in ASIC design environments, Linux scripting (Python, Perl, TCL), and semiconductor devices is highly valued, as is knowledge of chip packaging and board development concepts. Strong organizational, communication, and teamwork skills are essential, along with fluency in English.

If you’re interested in open-source development at IHP and would like to explore other aspects of our initiatives, we welcome you to send us an unsolicited application - let’s explore how you can contribute to our growing team!

Apply here: https://lnkd.in/eaf47U6t