[paper] anybody can design and build a chip

Krzysztof Herman, Norbert Herfurth, Tim Henkes, Sergei Andreev, Rene Scholz, Markus Müller, Mario Krattenmacher, Harald Pretl, and Wladyslaw Grabinski

On the Versatility of the IHP BiCMOS Open Source and Manufacturable PDK: 

A step towards the future where anybody can design and build a chip

IEEE Solid-State Circuits Magazine, vol. 16, no. 2, pp. 30-38, Spring 2024

DOI: 10.1109/MSSC.2024.3372907

Abstract: In this article, we introduce the first European open source process design kit (PDK), namely IHP-Open130-G2. We provide a concise history of the PDK itself and offer a brief comparison with some alternative open source PDKs, such as SKY130 and GF180MCU. The article also includes a process description and details on deliverables, offering insights into available devices, models, supported open source tools, and workflows. As the IHP-Open130-G2 is currently under development, we present key points outlining future activities. This aims to inform and attract users to join the open source silicon community. The concluding section of the article compares measurement results for active devices with compact model results. The article concludes with a cryptographic Internet protocol (IP) core based on IHP-Open130-G2 as an exemplary use case.

FIG: Silicon Proven Application: The final layout of the HEP custom cryptographic IP core.

[REF] “130nm BiCMOS open source PDK, dedicated for analog, mixed signal and RF design.” GitHub. Online: https://github.com/IHP-GmbH/IHP-Open-PDK

[paper] 5-DC-Parameter MOSFET Model

Deni Germano Alves Neto 1,3, Mohamedkhalil Bouchoucha 2,3, Gabriel Maranhão 1, Manuel J. Barragan 3, Márcio Cherem Schneider 1, Andreia Cathelin 2, Sylvain Bourdel 1

and Carlos Galup-Montoro 1

Design-Oriented Single-Piece 5-DC-Parameter MOSFET Model

IEEE Access; vol. 12 (2024)

DOI: 10.1109/ACCESS.2024.3417316

1 Department of Electrical and Electronics Engineering, FUSC, Florianópolis (BR)

2 STMicroelectronics, Crolles (F)

3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)

Abstract: This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than 20 % in the DC currents and 30 % in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4GHzlow-noise-amplifier in a 28nm FD-SOI CMOS technology. Obtained results in terms of S11, S21, NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.

 

Technology	130nm		28nm
Transistor	NMOS	PMOS	NMOS	PMOS
W/L (um/um) VTO (mV)	10/0.12 490	10/0.12 -478	1/0.06 389	1/0.06 -404
Is (uA)	11.78	9.39	3.15	0.76
n	1.41	1.46	1.15	1.01
σ	0.053	0.048	0.018	0.029
ς	0.007	0.031	0.039	0.024
δ	-	-	0.079	-0.076

FIG:  Conceptual structure of the ACM2 Model and its 6-DC parameters.

Acknowledgment: The authors would like to thank the STIC-AmSud multi national cooperative scientific program for supporting this research and STMicroelectonics and the Institute for High-Performance Microelectronics (IHP) for the design kits and silicon measurements. This work was supported in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (BR); in part by the Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BR); in part by the TIMA Laboratory, Grenoble (F) and in part by STMicroelectronics, Crolles, France.

Using LEGO as a Tool for Science Communication

Johannes Brantl1,2, Martin Dierolf1,2 and Franz Pfeiffer1,2,3,4

Using LEGO^® as a Tool for Science Communication: 

Design and Construction of a Model of the Munich Compact Light Source

Collection of Abstracts for the ICXS 2024 Workshop

1 Chair of Biomedical Physics, Department of Physics, TU Munich (D)

2 Munich Institute of Biomedical Engineering, TU Munich (D)

3 Department of Diagnostic and Interventional Radiology, TU Munich (D)

4 TUM Institute for Advanced Study, TU Munich (D)

Abstract : LEGO^® bricks are a versatile and engaging tool for science communication and outreach. By using LEGO^® to build miniaturized models of scientific facilities and instruments, researchers can educate the public and fellow investigators about complex scientific concepts in a fun and accessible way. In this work, we describe the construction of two large-scale LEGO^® models of the Munich Compact Light Source (MuCLS), a cutting-edge research facility that produces quasi-monochromatic high-intensity X-rays for various scientific applications.

Fig : Rendering of the Munich Compact Light Source LEGO^® model.

[June 18] Silicon Chip Industry Awareness Workshop

Silicon Chip Industry Awareness Workshop Seminar

Last Chance To Register ... Unlock Your Potential Today!

Join us on Tue 18 June at the Holiday Inn in Kensington, London, England, 9:30am to 4:00pm. Whether you are a non-technologist struggling with the jargon or a specialist looking to understand the overall industry structure, this workshop is for you.

Don't take our word for it … ask our past attendees. "Thank you for such an insightful class yesterday. It was the most useful training session I have had. I learned an incredible amount and I appreciate your time. What is so exciting about this field is that it is not only a lesson in physics but also chemistry, history, philosophy, geography, economics and so on."

Gain a competitive edge in the Semiconductor Industry by learning how the IC industry works from the science that enables silicon chips to be made from sand to the market fundamentals that drive applications and economics. Experience the industry through Listen, Discuss, See, Touch, and Learn activities and enjoy improved job satisfaction and operational efficiency.

Priced at just UK£795 plus 20 percent UK VAT per delegate, the fee includes copies of presentation materials, coffee breaks and lunch.  Workshops can also be held in-house for your added convenience and flexibility.  To preserve course integrity, space is limited, so don't wait – Secure Your Spot Today at: https://www.futurehorizons.com/page/12/silicon-chip-training

Past Attendee Comments
* "As a non-technologist, it was very beneficial to have these issues so clearly explained"
* "The seminar provided a good basis to understanding the industry"
* "It was GREAT! I can't remember a day of a similar density"
* "I finally understand how to recognize products & their use in technology"
* "This has helped me structure my thoughts & plans for the company"
* "It gave me deeper insight into the industry in a way difficult to obtain anywhere else"
* "This will be very useful when involved in our core business development discussions"

Book Your Place by Email

Please pass to your HR Department or a colleague if already attended or not suitable for you.

-- Sincerely -- Malcolm Penn, Chairman & CEO; 

Future Horizons; Registered Company: 4380991
Blakes Green Cottage, Sevenoaks, Kent TN15 0LQ, England
Tel: +44 (0)1732 740440

Follow us on Twitter @Future_Horizons and 

join our Linked In Group (http://uk.linkedin.com/in/malcolmpenn) 

and receive regular industry news, information and comments. 

[paper] CMOS-First MEMS-last integration

Aron Michael, Ian Yao-Hsiang Chuang, Chee Yee Kwok and Kazuo Omaki

Low-thermal-budget electrically active thick polysilicon for CMOS-First MEMS-last integration

Microsystems & Nanoengineering (2024) 10:75

DOI: 10.1038/s41378-024-00678-5

* UNSW, Sydney, NSW 2052, Australia

Abstract: Low-thermal-budget, electrically active, and thick polysilicon films are necessary for building a microelectromechanical system (MEMS) on top of a complementary metal oxide semiconductor (CMOS). However, the formation of these polysilicon films is a challenge in this field. Herein, for the first time, the development of in situ phosphorus-doped silicon films deposited under ultrahigh-vacuum conditions (~10E−9 Torr) using electron-beam evaporation (UHVEE) is reported. This process results in electrically active, fully crystallized, low-stress, smooth, and thick polysilicon films with low thermal budgets. The crystallographic, mechanical, and electrical properties of phosphorus-doped UHVEE polysilicon films are studied. These films are compared with intrinsic and boron-doped UHVEE silicon films. Raman spectroscopy, X-ray diffraction (XRD), transmission electron microscopy (TEM) and atomic force microscopy (AFM) are used for crystallographic and surface morphological investigations. Wafer curvature, cantilever deflection profile and resonance frequency measurements are employed to study the mechanical properties of the specimens. Moreover, resistivity measurements are conducted to investigate the electrical properties of the films. Highly vertical, high-aspect-ratio micromachining of UHVEE polysilicon has been developed. A comb-drive structure is designed, simulated, fabricated, and characterized as an actuator and inertial sensor comprising 20-μm-thick in situ phosphorus-doped UHVEE films at a temperature less than 500°C. The results demonstrate for the first time that UHVEE polysilicon uniquely allows the realization of mechanically and electrically functional MEMS devices with low thermal budgets.

Fig: Comb-drive fabrication: a Grow oxide; b deposit thick UHVEEPolySi; c electrical pads patterned; d pattern the comb-drive; e backside pattern; f DRIE of UHVEEPolySi; g STS ICP oxide and DRIE from backside; h Remove Cr using O2 plasma; i HF vapor etch

Acknowledgements: The authors wish to acknowledge the Australian National Fabrication Facility (ANFF) NSW node, the School of Photovoltaic & Renewable Energy Engineering (SPREE) and the Electron Microscope Unit at UNSW, where fabrication and film characterization were conducted. In addition, the authors acknowledge the financial support received from the School of Electrical Engineering & Telecommunications (EE) and UNSW Sydney.