Showing posts with label 5-DC-Parameter. Show all posts
Showing posts with label 5-DC-Parameter. Show all posts

Jul 3, 2024

[paper] 5-DC-Parameter MOSFET Model

Deni Germano Alves Neto 1,3, Mohamedkhalil Bouchoucha 2,3, Gabriel Maranhão 1, Manuel J. Barragan 3, Márcio Cherem Schneider 1, Andreia Cathelin 2, Sylvain Bourdel 1
and Carlos Galup-Montoro 1
Design-Oriented Single-Piece 5-DC-Parameter MOSFET Model
IEEE Access; vol. 12 (2024)
DOI: 10.1109/ACCESS.2024.3417316

1 Department of Electrical and Electronics Engineering, FUSC, Florianópolis (BR)
2 STMicroelectronics, Crolles (F)
3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)

Abstract: This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than 20 % in the DC currents and 30 % in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4GHzlow-noise-amplifier in a 28nm FD-SOI CMOS technology. Obtained results in terms of S11, S21, NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.
 
Technology 130nm28nm
Transistor NMOS PMOS NMOS PMOS
W/L (um/um)
VTO (mV)
10/0.12
490
10/0.12
-478
1/0.06
389
1/0.06
-404
Is (uA)11.78 9.39 3.15 0.76
n1.41 1.46 1.15 1.01
σ0.053 0.048 0.018 0.029
ς0.007 0.031 0.039 0.024
δ- - 0.079 -0.076

FIG:  Conceptual structure of the ACM2 Model and its 6-DC parameters.

Acknowledgment: The authors would like to thank the STIC-AmSud multi national cooperative scientific program for supporting this research and STMicroelectonics and the Institute for High-Performance Microelectronics (IHP) for the design kits and silicon measurements. This work was supported in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (BR); in part by the Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BR); in part by the TIMA Laboratory, Grenoble (F) and in part by STMicroelectronics, Crolles, France.