[paper] State Transitions in Autonomous Nonlinear Bistable Systems

Léopold Van Brandt and Jean-Charles Delvenne

Predicting State Transitions in Autonomous Nonlinear Bistable Systems

with Hidden Stochasticity

IEEE Control Systems Letters (L-CSS 2024)

* UCLouvain, Louvain-la-Neuve (B)

Abstract: Bistable autonomous systems can be found in many areas of science. When the intrinsic noise intensity is large, these systems exhibits stochastic transitions from one metastable steady state to another. In electronic bistable memories, these transitions are failures, usually simulated in a Monte-Carlo fashion at a high CPU-time price. Existing closed form formulas, relying on near-stable-steady-state approximations of the nonlinear system dynamics to estimate the mean transition time, have turned out inaccurate. Our contribution is twofold. From a unidimensional stochastic model of overdamped autonomous systems, we propose an extended Eyring-Kramers analytical formula accounting for both nonlinear drift and state-dependent white noise variance, rigorously derived from Itô stochastic calculus. We also adapt it to practical system engineering situations where the intrinsic noise sources are hidden and can only be inferred from the fluctuations of observables measured in steady states. First numerical trials on an industrial electronic case study suggest that our approximate prediction formula achieve remarkable accuracy, outperforming previous non-Monte-Carlo approaches.

Fig: (a) SRAM bitcell retaining a logical 0 or 1 encoded on two complementary node voltages (v2 and v1) as low and high levels VL and VH. The retained state is stabilised by a feedback loop implemented by two cross-coupled inverters. An inverter is a nonlinear time-invariant system producing a high VH (resp. low VL) output when its input is maintained at constant low VL (resp. high VH), yet with internal dynamics and intrinsic noise.

(b) Transient noise simulation at supply voltage VDD = 70 mV (adapted from [1]). Intrinsic noise-induced stochastic state transitions (bit flips VL ↔ VH) are observed. VM denotes the threshold voltage corresponding to the unstable state. For the illustrated case, the bistable system is symmetrical in the sense that two inverters are identical, making the two steady states equiprobable and the transitions VL ↔ VH rates equal.

Acknowledgements: The work has been partially supported by the Research Project "Thermodynamics of Circuits for Computation" of the National Fund for Scientific

Research (FNRS) of Belgium.

[Latch-Up] IHP Open Source PDK

IHP Open Source PDK:

Announcement, Setup, Current State and Experiences, and look ahead

Frank Vater, IHP Frankfurt (Oder), Germany

Latch-Up 2024 video

Abstract: Main focus of this talk is the SG13G2 Open Source PDK for IHP 130nm BiCMOS technology. The current state of our activities will be given for the analogue as well as for the digital PDK including design flow with open source tools. Some more details on first experiences for schematic driven design, simulation, layout, DRC and LVS will be pointed out. Furthermore, already known challenges analogue and digital design flow and open issues on open source tool chain will be addressed. The talk will be closed with a road map for future work.

Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.

Produced by NDV: @nextdayvideo
OpenHardware Sat Apr 20 16:20:00 2024 at b45r230

[paper] Compact Model of IDG BEOL Transistor for Capacitorless Memory

Lihua Xu, Kaifei Chen, Zhi Li, Yue Zhao, Lingfei Wang and Ling LiPhysics-Based 

Compact Model of Independent Dual-Gate BEOL-Transistors

for Reliable Capacitorless Memory

in IEEE Journal of the Electron Devices Society

DOI: 10.1109/JEDS.2024.3393418  

School of Microelectronics, University of Science and Technology of China, Hefei (CN)
State Key Lab of FTIC, Institute of Microelectronics of Chinese Academy of Sciences, Beijing (CN)
University of Chinese Academy of Sciences, Beijing (CN)

Abstract: Capacitorless DRAM architectures based on Back End-of-Line (BEOL)-transistors are promising for long retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to ~ 50 nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.

Fig: (a) Schematic illustration of the IDG a-IGZO FETs with a thickness of ~5nm. (b) Agreement between analytical and numerical results of back gate surface potentials at different VDS with errors in the inset. VTG & VBG denotes DG synchronized-sweep with the same voltage.

Acknowledgements: This work was supported in part by National key research and development program (Grant Nos. 2021YFB3600704), the National Natural Science Foundation of China (Grant Nos. 62274178, 92264204), CAS Interdisciplinary Innovation Team [JCTD-2022-07].

[IC Design] Single Photon Counting ASIC for Synchrotron Applications

Ultra-Fast Single Photon Counting ASIC for Fast Synchrotron Applications

Dr hab. inż Piotr Kmon

AGH University, Cracow, Poland

European Synchrotron Radiation Facility (ESRF), Grenoble, France

Abstract: The SPHIRD (Small Pixel High Rate photon counting Detector) project is an R&D study to investigate how far the photon counting X-ray hybrid pixel detector technology can go, regarding photon rate and spatial resolution. A goal was to boost by 30 times the count-rate capabilities of existing detectors of similar pixel size. SPHIRD targets that figure by designing fast front end electronics, by including pile-up compensation techniques in the pixel logic, and by implementing smaller pixels. Each pixel contains fast front-end analog electronics (pulse width is only 18ns) with base-line holder (BLH), a set of discriminators (with offset trimming blocks), ripple counters, and digital blocks. The pixel architecture allows also for operation in conventional mode (STDC) and with different pulse pile-up compensation methods (these are voltage and time based methods named VDIS, TDIS, and FPHC respectively).

Fig: Schematic idea of the recording channel and the chip photo with mounted detector

Technology: TSMC 40nm GP; Die Size: 3.2mm x 3.5mm

Acknowledgements: The chip design was realized by P. Grybos, R. Kleczek, P. Otfinowski, and P. Kmon (AGH) while synchrotron experiments were conducted by P. Fajarado, D. Magalhaes and M. Raut.

References
[1] P. Grybos,et.al., “SPHIRD–Single Photon Counting Pixel Readout ASIC With Pulse Pile-Up Compensation Methods”, IEEE IEEE Transactions on Circuits and Systems--II: Express Briefs, vol. 70, no. 9, 2023, p. 3248-3252.
[2] D. Magalhaes et al., Very High Rate X-ray Photon Counting 2D Detectors with Small Pixels: the SPHIRD Project. 2022 IEEE NSS-MIC-RTSD Conference Proceedings.

[CNM25] Academic Process Design Kit

The aim of this academic process design kit (APDK) is to introduce circuit designers to the top-down design methodology of mixed-signal full-custom integrated circuits (ICs) in CMOS technologies. For this purpose, the following freely available electronic design automation (EDA) tools are proposed for both the schematic and the physical IC design. The APDK incorporates all the required technological information for the simple 2.5um 1P2M PiP CMOS technology (CNM25) from IMB-CNM(CSIC). Anyway, this APDK can be easily customized to extend its coverage to more complex CMOS technologies.

News 2024.04.09:

APDK release version 2024_04_09
+ Update to Glade 6.x series (Qt6)
+ Screenshots

REF: Poster at IEEE ISCAS 2017 in Baltimore, MD, USA.

CONTACT: 

Francesc Serra-Graells

www.cnm.es/users/pserra

tel: +34 93 594 77 00

fax: +34 93 580 02 67

IMB-CNM (CSIC)

Campus UAB Bellaterra

08193 Cerdanyola del Vallès, SPAIN