[PhD] ULTRARAM™ at Lancaster University

Lancaster University, Physics Department has three open PhD Projects, Programmes & Scholarships

• Scaling ULTRARAM™ on FindAPhD.com
  The PhD project will further advance the development of ULTRARAM™ memory. ULTRARAM™ is an ultra-efficient, multi-award-winning memory technology that combines the non-volatility of flash with the speed and endurance of dynamic random access (DRAM).
• Vertical-cavity surface-emitting lasers for below-screen consumer (and other) applications at Lancaster University on FindAPhD.com
  The PhD project will further develop a patented approach to implementing vertical-cavity surface-emitting lasers (VCSELs) operating at telecoms wavelengths
• Novel compound-semiconductor logic for computing applications on FindAPhD.com
  The PhD project will further develop a patent-pending alternative approach to digital logic that abandons the CMOS paradigm underpinning computing

Supervisor: Prof. M. Hayne

Application deadline: 29 February 2024 // Competition Funded PhD Project (UK Students Only)

Chips JU Launch Event

 

https://www.chipsjulaunchevent.eu/

Agenda Day 1: Embracing the voice of stakeholders

12:00 - 14:30	Registration
13:00 - 15:30	Networking lunch and exhibition "Walk of Fame" opening and guided tour
15:30 - 15:40	Welcome and opening, Jari Kinaret, Executive Director of the Chips JU
15.40 - 16:00	Keynote speech, Thierry Breton, European Commissioner for Internal Market
16:00 - 16:20	Intro speeches "EU strategic autonomy and economic security"
	Nikolai Setzer, CEO, Continental AG
	Jaime Martorell, Special Commissioner for Microelectronics and Semiconductors, Spain
16:20 - 17:20	1st Panel discussion with a moderator
	Thomas Skordas, DDG, CNECT, European Commission
	Pierre Barnabé, CEO, Soitec
	Roger Dassen, CFO, ASML
	Luc Van den hove, President and CEO, imec
	Frédérique Le Grévès, President & CEO, STMicroelectronics France
	Cinzia Silvestri, CEO, Bi/ond
	Alain Jarre, Chairman and CEO, RECIF Technologies
17:20 - 17:40	Coffee break
17:40 - 18:00	Intro speeches "Maintaining and boosting European technology leadership"
	Jochen Hanebeck, CEO, Infineon Technologies AG
	Jo Brouns, Flemish Minister for Economy, Innovation, Work, Social Economy, and Agriculture
18:00 - 19:00	2nd Panel discussion with a moderator
	Signe Ratso, Deputy Director-General, DG RTD, European Commission
	European Semiconductor Board Member (name tbc)
	Stefan Finkbeiner, CEO, Bosch Sensortec GmbH
	Maurice Geraets, Executive Director, NXP Semiconductors Netherlands B.V.
	Sébastien Dauvé, CEO, CEA-Leti
	Eva Maydell, Member of the European Parliament
	Joost van Kuijk, CEO/CMO, Adimec
19:00 - 19:05	Closing remarks by the moderator
19:15	Shuttle bus to the social event venue
20:00 - 22:30	Social event and walking dinner “Art & History Museum of Belgium”

Day 2 Part 1: Presentation of the Initiative

08:00 - 09:00	Registration & welcome coffee
09:00 - 09:10	Intro speech by Lucilla Sioli, Director DG CNECT.A, European Commission
09:10 - 09:40	New advanced pilot lines: Yves Gigase, Head of Programmes, Anton Chichkov, Programme Officer, Chips JU
09:40 - 09:55	Network of competence centre: Yves Gigase, Head of Programmes, and Anton Chichkov, Programme Officer, Chips JU
09:55 - 10:10
	Cuting-edge quantum chips: Gustav Kalbe, acting Director DG CNECT C, and
	Christian Trefzger, Policy Officer, DG CNECT, European Commission
10:10 - 10:25	Chips Fund: EC, EIB, EIC joint presentation
10:25 - 10:55	Q&A
10:55 - 11:25	Coffee break, networking and exhibition
11:25 - 12:15	Interactive session on Advanced design platform: Marco Ceccarelli and Matihew Xuereb, Policy Officers, DG CNECT, European Commission
12:15 - 13:40	Networking lunch.

Day 2 Part 2: Chips JU R&I Programme

13:40 - 13:50	Intro speech by Jean-Luc di Paola-Galloni, Chair of the Chips JU Private Members Board
13:50 - 14:50	3rd Panel discussion with a moderator
	Lucilla Sioli, Director, DG CNECT.A, European Commission
	Michael Paulweber, Director Global ITS Research & Technology, AVL List
	Régis Hamelin, CTO, Blumorpho
	Francis Balestra, Director of Research CNRS
	Ferdinand Bell, Head of Public Collaborative Programs, NXP Semiconductors, Germany GmbH
	Christoph Kutier, Vice-Chair, Fraunhofer Microelectronics Group/FMD
	Bert de Jonge, CEO, VERUM
14:50 - 15:20	ECS SRIA 2024 – What is new? Patrick Cogez, Technical Director, AENEAS IA
15:20 - 15:50	Upcoming Chips JU calls and focus topics
	Yves Gigase, Head of Programmes, and Anton Chichkov, Programme Officer, Chips JU
15:50 - 16:00	Closing remarks Jari Kinaret, Executive Director of the Chips JU
16:00 - 17:30	Coffee break, networking and exhibition

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions

[C4P] LAEDC 2024

CALL FOR PAPERS & POSTERS

LAEDC 2024 R&D topics of interest include, but are not limited to:

All electron-based devices Electron Devices for Quantum Computing RF-MMW-5G Semiconductor-, MEMS- and Nanotechnologies Packaging, 3D integration Sensors and actuators Display technology Modeling and simulation Reliability and yield Device characterization Reliability Agrivoltaics

Flexible electronics Biomedical Devices Circuit-device interaction Novel materials and process modules Technology roadmaps Electron device engineering education Electron device outreach Optoelectronics, photovoltaic and photonic devices and systems Humanitarian Projects STEM Initiatives Energy harvesting 2D Materials and Devices

IMPORTANT DATES:

• Paper submission deadline: January 15, February 19, 2024
• Author notification: April 1, 2024
• LAEDC Conference Dates: MAY 8-10 2024

SPECIAL SESSIONS:

• MOS-AK Workshop
• IEEE EDS MQ
• LAEDC Summer School
• IEEE WIE/YP Session
• Humanitarian Technology Session

ABOUT GUATEMALA:

Guatemala, country of Central America. The dominance of an Indigenous culture within its interior uplands distinguishes Guatemala from its Central American neighbours. The origin of the name Guatemala is Indigenous, but its derivation and meaning are undetermined. Some hold that the original form was Quauhtemallan (indicating an Aztec rather than a Mayan origin), meaning “land of trees,” and others hold that it is derived from Guhatezmalha, meaning “mountain of vomiting water” - referring no doubt to such volcanic eruptions as the one that destroyed Santiago de los Caballeros de Guatemala (now Antigua Guatemala), the first permanent Spanish capital of the region’s captaincy general. The country’s contemporary capital, Guatemala City, is a major metropolitan centre. Quetzaltenango, in the western highlands, is the nucleus of the Indigenous population.

Chipsalliance Technology Update - Nov. 2023

November 9, 2023

Check out the presentations below, and watch the replay here

• Project Open Se Cura (slides)
  Kenny Vassigh, Bangfei Pan, Cindy Liu, Kai Yick, Google, Michael Gielda, Antmicro, Brian Murray, Verisilicon
• Caliptra Workgroup Update (slides)
  Andres Lagar-Cavilla, Google
• Enabling UVM testbenches in Verilator (slides)
  Michael Gielda, Karol Gugala, Antmicro
• FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development (slides)
  Olof Kindgren, Qamcom
• CHIPYard: An Open Source RISC-V Design Framework (slides)
  Sagar Karandikar, U.C. Berkeley

Watch the Replay