[paper] STT-MTJ Device Model

Haoyan Liu and Takashi Ohsawa
General-Purpose STT-MTJ Device Model Based on the Fokker-Planck Equation
IEEE Transactions On Nanotechnology, VOL. 22, 2023 659 A
DOI: 10.1109/TNANO.2023.3322468.

Graduate School of Information, Production and Systems, Waseda University (J)

Abstract: A thermally agitated device model of spin-transfer torque magnetic tunnel junction (STT-MTJ) based on the Fokker-Planck equation is proposed which is implemented into HSPICE by using Verilog-A. We compared different techniques of finite difference method (FDM) and analyzed the impact of the solvers on computational efficiency and accuracy. A framework is proposed which traces dynamics of a particular STT-MTJ’s angle between the magnetic moments of the free and the pinned layers and makes the model applicable to a wide range of circuits. The model was applied to the 4T2MTJ memory cell array and a leaky integrate and-fire (LIF) neuron circuit to validate the stochastic switching characteristic and the angle prediction function. In the memory array simulations, the CPU time consumption for this model is 1/30 of the model which is based on the stochastic Landau-Lifshitz Gilbert-Slonczewski equation.

Fig: (a) Structure of 1T1MTJ synapse. (b) Binary weights in 10 neurons and an input digit ‘9’ of spiking neural network (surrounded by the dotted square) used for the experiment shown. Each digit is a 28×28 matrix. Each figure shows two output spikes fired in the neurons representing ‘0-9’. The total spike numbers of the neurons which represent 0-9 are 2, 3, 4, 3, 4, 4, 4, 4, 4 and 9. 

Acknowledgement: This work was supported in part by Synopsys Corporation, in part by JSPS KAKENHI under Grant JP20K04626, in part by VLSI Design and Education Center (VDEC), University of Tokyo with collaboration with Cadence Corporation, and in part by the cooperation of organization between Kioxia Corporation and Waseda University.

[chapter] Extraction for a 65nm FG Transistor.

[chapter] Cong, T.D., Hoang, T. (2023). A Methodology of Extraction DC Model for a 65 nm Floating-Gate Transistor. 

In: Dao, NN., Thinh, T.N., Nguyen, N.T. (eds) Intelligence of Things: Technologies and Applications. ICIT 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 187. Springer, Cham. https://doi.org/10.1007/978-3-031-46573-4_19

Abstract: Floating-gate Metal-Oxide Semiconductor (MOS) has been investigated and applied in many applications such as artificial intelligence, analog mixed-signal, neural networks, and memory fields. This study aims to propose a methodology for extracting a DC model for a 65 nm floating-gate MOS transistor. The method in this work uses the combination architecture of MOS transistor, capacitance, and voltage-controlled voltage source which can archive a high accuracy result. Moreover, the advantage of the method is that the MOS transistor was a completed model which enhances the flexibility and accuracy between a fabricated device and modeled architecture. In our work, the industrial standard model Berkeley Short-channel IGFET Model (BSIM) 3v3.1, level 49 was deployed, and the DC simulation was obtained with the use of LTspice tool.

[book] Microelectronic Circuits

Sedra, Adel S., Smith, Kenneth Carless, Carusone, 

Tony Chan, Gaudet, Vincent. 

Microelectronic Circuits. 

United Kingdom: Oxford University Press, 2020

Circuits by Sedra and Smith has served generations of electrical and computer engineering students as the best and most widely-used text for this required course. Respected equally as a textbook and reference, "Sedra/Smith" combines a thorough presentation of fundamentals with an introduction to present-day IC technology. It remains the best text for helping students progress from circuit analysis to circuit design, developing design skills and insights that are essential to successful practice in the field. Significantly revised with the input of two new coauthors, slimmed down, and updated with the latest innovations, Microelectronic Circuits, Eighth Edition, remains the gold standard in providing the most comprehensive, flexible, accurate, and design-oriented treatment of electronic circuits available today.

Appendix

• B. SPICE Device Models and Design with Simulation Examples

Model files for representative CMOS technologies are provided below:

• 0.8 um CMOS
• 0.35 um CMOS
• 0.18 um CMOS
• 45 nm CMOS
• 7nm FinFET

 

[paper] Sub-THz HICUM for SiGe HBTs

Soumya Ranjan Panda, Thomas Zimmer, Anjan Chakravorty, Nicolas Derrier

and Sebastien Fregonese

Exploring Compact Modeling of SiGe HBTs in Sub-THz Range With HICUM

in IEEE TED, DOI: 10.1109/TED.2023.3321017.

IMS laboratory, CNRS, University of Bordeaux (F)
Department of Electrical Engineering, IIT Madras (IN)
STMicroelectronics, 38920 Crolles (F)

Abstract : This study delves deeper into the high frequency (HF) behavior of state-of-the-art sub-THz silicon germanium heterojunction bipolar transistors (SiGe HBTs) fabricated with 55 nm BiCMOS process technology from STM. Using measurement data, calibrated TCAD simulations, and compact model simulations, we present a comprehensive methodology for extracting several HF parameters (related to parasitic capacitance partitioning and nonquasi-static effects) of the industry standard model, HICUM. The parameter extraction strategies involve thorough physics-based investigation and sensitivity analysis. The latter allowed us to precisely evaluate the effects of parameter variations on frequency dependent characteristics. The accuracy of the finally deployed model is tested by comparing the model simulation with measured small-signal two-port parameters of SiGe HBTs up to 330 GHz.

FIG: a.)  TEM image of the SiGe HBT device; b.) 2D TCAD structure simulation; c.) Large signal equivalent circuit of HICUM L2 compact model; d.) and e.) adjunct networks for vertical NQS effects

Acknowledgment: The authors would like to acknowledge Dider Celi, STM, for valuable discussion about the compact modeling of heterojunction bipolar transistors (HBTs), and they also like to thank STM for providing the silicon wafers. This work was supported by NANO2022 Important Project of Common European Interest Project (IPCEI), and SHIFT Grant ID 101096256.

[paper] Lorentzian noise spectra in compact models

Nikolaos Makris*†, Loukas Chevas* and Matthias Bucher*

Verilog-A based implementation of Lorentzian noise spectra in compact models

26th International Conference on Noise and Fluctuations - ICNF

17th-20th October 2023 - Grenoble - France

DOI: 10.1109/ICNF57520.2023.10472771

* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece        European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece

Abstract:In this paper, a simple Verilog-A implementation of Lorentzian noise spectra is introduced that can be used in compact models for the frequency-domain simulation of low-frequency noise in electronic devices. For this purpose, a thermal noise source is combined with a low-pass filter as realized using laplace_nd Verilog-A function in order to achieve Lorentzian noise behavior. This modeling approach can be implemented in any Verilog-A compact model and provides the means for bias-dependent Lorentzian trap modeling. This approach is evaluated in commercial simulator. Application examples are provided to demonstrate the capabilities of this approach.

FIG: Bias dependent model implemented in the EKV3 MOSFET model

Acknowledgements: This work was co-funded by the ERASMUS+ Programme of the European Union (Contract number: 101004049 - EURECA-PRO - EAC-A02-2019 / EAC-A02-2019-1). This research has been co-financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH - CREATE - INNOVATE (project code: T2EDK-00340).