Creating sub-1-nm gate lengths for MoS2 transistors https://t.co/7E4V3Bp3Bz #semi https://t.co/1pwI2wUajO
— Wladek Grabinski (@wladek60) Mar 14, 2022
from Twitter https://twitter.com/wladek60
March 14, 2022 at 05:50PM
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Mar 14, 2022
Creating sub-1-nm gate lengths for MoS2 transistors
from Twitter https://twitter.com/wladek60
March 14, 2022 at 05:50PM
via IFTTT
Mar 9, 2022
[mos-ak] [2nd Announcement and C4P] Spring MOS-AK Workshop on April 1, 2022 (online)
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
Spring MOS-AK Workshop
April 1, 2022 (online)
2nd Announcement and C4P
Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
W.Grabinski for Extended MOS-AK Committee- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source (FOSS) TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, Organic TFT, CMOS and SOI-based memory
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
- Technology R&D, DFY, DFT and reliability/aging IC designs
- Foundry/Fabless Interface Strategies
Online Abstract Submission to be open (any related enquiries can be sent to absttracts@mos-ak.org)
Online Event Registration to be open (any related enquiries can be sent to registration@mos-ak.org)
Important Dates:
- Call for Papers: Feb. 2022
- 2nd Announcement: March 2022
- Final Workshop Program: March 22, 2022
- Spring MOS-AK Workshop: April 1, 2022
WG090322
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Silicon Nitride PICs | March 21-22 | Onsite or Online
|
Mar 8, 2022
[paper] p-Type Doped Silicene-based
Mu Wen Chuan, Munawar Agus Riyadi, Afiq Hamzah, Nurul Ezaila Alias, Suhana Mohamed Sultan, Cheng Siong Lim, Michael Loong Peng Tan
Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model
PLoS ONE 17(3): e0264483.: March 3, 2022
DOI: 10.1371/journal.pone.0264483
Universiti Teknologi Malaysia, Skudai, Johor, Malaysia
Diponegoro University, Semarang, Indonesia
Abstract: Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.
Fig: Schematic diagrams of AlSi3 FET: (a) the structure and
(b) the ToB nanotransistor circuit model.
Acknowledgements: 1.) Michael Tan Loong Peng - Ministry of Higher Education (MOHE) of Malaysia through the Fundamental Research Grant Scheme(FRGS/1/2021/ STG07/ UTM/02/3); The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. 2.) Munawar Agus Riyadi - World Class Research Universitas Diponegoro (WCRU) 2021 Grant no. 118-16/UN7.6.1/PP/2021; The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.
Mar 7, 2022
[paper] Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs
Kerim Yilmaz, Benjamín Iñíguez, François Lime, and Alexander Kloes
Cryogenic Temperature and Doping Analysis of Source-to-Drain Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs
IEEE TED, Vol. 69, No. 3, March 2022
DOI: 10.1109/TED.2022.3145339
NanoP, THM Giessen (D)
DEEEA, Universitat Rovira i Virgili, Tarragona (SP)
Abstract:This work analyzes the impact of doping concentration on the temperature-dependent subthreshold current and swing saturation due to direct source-to-drain tunneling (DSDT) in short-channel silicon nanosheet (SiNS) metal–oxide–semiconductor field-effect transistors (MOSFETs). Furthermore, their influence on the drain-induced barrier lowering (DIBL) effect is investigated. Special attention is paid to the importance of the Fermi level and the average tunneling energy, whose energetic positions and distance from each other in the band diagram has a significant role in the temperature-dependent saturation behavior of the subthreshold current and swing, as well as the value of DIBL. Furthermore, we model and present with device simulation the existence of two merging subthreshold swings (Ssth) and DIBL effects with increasing gate bias at cryogenic temperatures. The merging is achieved by the superposition of the DSDT and thermionic emission (TE) current, which originate from their own dominated and visibly separated gate-bias regions.
FIG: First subband energy of the conduction band together with a color plot showing the electron energy dependent normalized tunneling and TE current densities at an operating
temperature T0=300K with S/D doping of Ns/d=1E20cm^−3
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