[paper] Metal-Oxide Memristor Compact Model

Eugeny Ryndin,Natalia Andreeva and Victor Luchinin

Compact Model for Bipolar and Multilevel Resistive Switching in Metal-Oxide Memristors

Micromachines 2022, 13(1), 98; Special Issue Amorphous Oxide Semiconductor-Based Memristive Devices and Thin-Film Transistors

DOI: 10.3390/mi13010098

  
* Electrotechnical University “LETI”, Saint Petersburg (RU)

Abstract The article presents the results of the development and study of a combined circuitry (compact) model of thin metal oxide films based memristive elements, which makes it possible to simulate both bipolar switching processes and multilevel tuning of the memristor conductivity taking into account the statistical variability of parameters for both device-to-device and cycle-to-cycle switching. The equivalent circuit of the memristive element and the equation system of the proposed model are considered. The software implementation of the model in the MATLAB has been made. The results of modeling static current-voltage characteristics and transient processes during bipolar switching and multilevel turning of the conductivity of memristive elements are obtained. A good agreement between the simulation results and the measured current-voltage characteristics of memristors based on TiOx films (30 nm) and bilayer TiO2/Al2O3 structures (60 nm/5 nm) is demonstrated.

Fig: Structures of the memristors based on TiOx (a) and TiO2/Al2O3 (b) films.

Acknowledgements: This research was funded by the Ministry of Science and Higher Education of the Russian Federation, Grant No FSEE-2020-0013.

[paper] Pseudo-morphic PHEMT: Numerical Simulation Study

Khaouani Mohammed, Hamdoune Abdelkader, Guen Ahlam Bouazza, Kourdi Zakarya, Hichem Bencherif

An Improved Performance of Al0.25Ga0.75N/AlN/GaN/Al0.25Ga0.75N Pseudo-morphic High Electron Mobility Transistor (PHEMT): 

Numerical Simulation Study

IC-AIRES 2021. Lecture Notes in Networks and Systems, vol 361. Springer

DOI: 10.1007/978-3-030-92038-8_80

1. Hassiba Benbouali, Chlef, Algeria

2. University of Abou-Bakr Belkaid, Tlemcen, Algeria
3. Center Exploitation Satellite Communications Agency of Space Oran, Algeria
4. University of Mostefa Benboulaid, Batna, Algeria 

Abstract: In this paper a 9nm T-shaped gate length, Pseudo-morphic High Electron Mobility Transistor (pHEMT AlGaN/AlN/GaN/AlGaN) is studied; we use TCAD software. DC, AC and RF performances assessment allow to exhibit interesting results such as a maximum drain current IDSmax=35mA at VGS=0V, a knee voltage Vknee=0.5V with ON-resistance Ron=0.8Ω-mm, a sub-threshold swing of 75mV/decade, a maximum transconductance value gm=160mS/mm, a DIBL of 36mV/V, a drain lag of 8.5%, a cut-off frequency of 110GHz, a maximum oscillation frequency of 800GHz, and very suitable breakdown voltage VBR of 53.1V. This device can be used in radar, high power and amplifier applications.

[paper] Compact Modelling of Si Nanowire/Nanosheet MOSFETs

A. Cerdeira¹, M. Estrada¹, and M. A. Pavanello²

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Semiconductor Science and Technology, vol. 37, no. 2, p. 025014, Jan. 2022.

DOI: 10.1088/1361-6641/ac45c0

   

1 Centro de lnvestigacién y de Estudios Avanzados del IPN, Mexico City, Mexico
2 Centro Universitario PEI, Sao Bernardo do Cainpo, Sao Paulo, Brazil

Abstract: In this paper, three-dimensional technology computer aided design simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in nanowire and nanosheet structures, are practically same. This characteristic makes it possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the symmetric doped double-gate model (SDDGM) model to nanowires and nanosheets metal-oxide-semiconductor field effect transistors, with no need to include new parameters. The model SDDGM is validated for this application using several measured and simulated structures of nanowires and nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SPICE circuit simulator.

Fig: a.) Normalized measured and modelled transfer characteristics of stacked transistor in the linear region at VDS=0.025V and in saturation region at VDS=0.75V; b.) Output characteristic and conductance at VGS=1V.

Acknowledgments: The authors are grateful to CEA—Leti for providing the exper- imental samples used in this paper. This work was supported by the CONACYT project 236887, CNPq, Sao Paulo Research Foundation (FAPESP) Grants 2015/ 1049 1-7 and 2019/ 15500- 5, and the IBM/STMicroelectronics/Leti Joint Development Alliance.

 

A new development method for flexible electronics

A new development method for flexible electronics https://t.co/TnLxEzxGrt #semi https://t.co/TzIHEsPxxd

— Wladek Grabinski (@wladek60) Jan 7, 2022

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January 07, 2022 at 08:20PM
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[paper] RTN of a 28-nm Cryogenic MOSFET

HeeBong Yang, Marcel Robitaille, Xuesong Chen, Hazem Elgabra, Lan Wei, Na Young Kim

Random Telegraph Noise of a 28-nm Cryogenic MOSFET in the Coulomb Blockade Regime

IEEE Electron Device Letters, vol. 43, no. 1, pp. 5-8, Jan. 2022

DOI: 10.1109/LED.2021.3132964.

  

* Institute for Quantum Computing, Waterloo Institute for Nanotechnology (CA)

Abstract: We observe rich phenomena of two-level random telegraph noise (RTN) from a commercial bulk 28-nm p-MOSFET (PMOS) near threshold at 14 K, where a Coulomb blockade (CB) hump arises from a quantum dot (QD) formed in the channel. Minimum RTN is observed at the CB hump where the high-current RTN level dramatically switches to the low-current level. The gate-voltage dependence of the RTN amplitude and power spectral density match well with the transconductance from the DC transfer curve in the CB hump region. Our work unequivocally captures these QD transport signatures in both current and noise, revealing quantum confinement effects in commercial short-channel PMOS even at 14 K, over 100 times higher than the typical dilution refrigerator temperatures of QD experiments (< 100 mK). We envision that our reported RTN characteristics rooted from the QD and a defect trap would be more prominent for smaller technology nodes, where the quantum effect should be carefully examined in cryogenic CMOS circuit designs.

Fig: (a) The trapping behaviors are illustrated with empty trap (solid line) and occupied trap (dashed line) across the hump area of the |ID| -|VGS| sweep. (b) The current power spectral density (PSD) of the discretized data with the 1/f2 PSD guideline in red.

Acknowledgment: J. Watt and C. Chen in Intel for samples, A. Malcolm for early work, and J.Baugh for helpful discussions are appreciated.