[paper] ACM Model for CMOS Analog Circuits Hand Design

Ademirde Jesus Costa^ab, Eliyas Mehdipour^b, Edson PintoSantana^b,

and Ana Isabela Araújo Cunha^b

Application of Improved ACM Model to the Design by Hand of CMOS Analog Circuits

Microelectronics Journal

Available online 16 November 2021, 105309

DOI: 10.1016/j.mejo.2021.105309

   
a Instituto Federal da Bahia, Santo Amaro, Brazil
b DEEC, Escola Politécnica, Universidade Federal da Bahia, Salvador, Brazil

Abstract: This work aims to provide solutions and perspectives for CMOS analog designers by reducing the time spent in iteratively dimensioning the devices and simulating the circuits. For this purpose, by-hand design methodologies for a few analog cells are proposed employing a MOSFET compact model which has been earlier improved by adding sub-models for some second order effects. A semiempirical sub-model and characterization method is presented for the Early voltage, thus enhancing the set of model equations for hand calculations. The accomplishment of several by-hand design examples and the comparison between simulation results and specifications succeeded in demonstrating the usefulness and advantages of using the improved MOSFET compact model in the proposed methodologies.

Fig: gm/Id Plot

Nanorennes (CNRS)

 

Nanorennes was created in 2007 as a regional micro-technological platform, labelled by french national center of research and science (CNRS). This platform gathers on the same institute the know-how and human beings dedicated to the fabrication of nano-micrometer sized devices, related to two research laboratories located in Rennes : IETR-GM (microelectronic group) and FOTON-OHM (photonic group).

[paper] TFT XNOR/XOR Circuit

E. Bestelink, O. de Sagazan*, I. S. Pesch and R. A. Sporea

Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors

in IEEE TED, vol. 68, no. 10, pp. 4951-4955, Oct. 2021,

DOI: 10.1109/TED.2021.3103491.

  

Advanced Technology Institute, University of Surrey (UK)

* IETR-DMM-UMR6164, University of Rennes (F)

Abstract: A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations.

Fig: Micrograph of fabricated microcrystalline MMT devices and circuits. Inset: individual MMT devices with single device (MMT) and two source control gates (SUMFGMMT). Scale bars: 500μm.

Acknowledgement: Devices were fabricated on the NanoRennes platform.

CCBY - IEEE is not the copyright holder of this material. 

My Story of Raja Manickam, CEO of OSAT, Tata Electronics

For the November issue, Electronicsforu.com Network shares My Story of Raja Manickam who is CEO of OSAT, Tata Electronics.

CLICK HERE to read it.

Rahul Chopra Editor,

Electronicsforu.com Network | EFY Group | New Delhi | India |

[mos-ak] 2nd Announcement and C4P] 14th International MOS-AK Workshop Silicon Valley, Dec. 17, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

14th International MOS-AK Workshop

Silicon Valley, Dec. 17, 2021

2nd Announcement and C4P

Together with local host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 14th International MOS-AK Workshop Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on Dec.17, 2021, in timeframe of IEDM and Q4 CMC Meetings.

Planned virtual 14th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies

Online Abstract Submission to be open (any related enquiries can be sent to abstracs@mos-ak.org)

Online Event (any related enquiries can be sent to register@mos-ak.org)

Important Dates: 

• Call for Papers: Oct. 2021
• 2nd Announcement: Nov. 2021
• Final Workshop Program: Dec.2 2021
• MOS-AK Workshop: Dec.17, 2021
  in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski for Extended MOS-AK Committee

WG171121

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