[paper] Emerging 2D Organic-Inorganic Heterojunctions

KePei¹ TianyouZhai¹

Emerging 2D Organic-Inorganic Heterojunctions

Cell Reports Physical Science, Vol. 1, Issue 8, 2020, 100166

DOI: 10.1016/j.xcrp.2020.100166

¹State Key Laboratory of Material Processing and Die and Mould Technology, School of Materials Science and Engineering, HUST, Wuhan 430074, PRC

Abstract: The unique properties of two-dimensional (2D) materials have boosted intensive interests in combining distinct 2D materials into van der Waals heterojunctions for novel device structures. The organic-inorganic heterojunctions, integrating atomically thin inorganic materials with an unlimited variety of organic molecules, provide an ideal platform for broader, superior, and on-demand functional applications by incorporating customized organic molecules that particularly exhibit decent optoelectronic properties, promising scalability and remarkable flexibility. In this Review, emerging 2D organic-inorganic heterojunctions from the perspectives of materials, manufacturing, structures, and interfaces, as well as recent progress in functional applications, are provided. Two prototypical construction approaches are summarized—epitaxy growth and molecular doping—followed by four directions of device applications, including electronic device, optoelectronic device, energy harvesting device, and memory and neuromorphic device. Finally, the frontier challenges and future outlook associated with the organic-inorganic heterojunctions are highlighted, which is critical for the further development of this cross-fertilized research field.

Figure: Overview of 2D Organic-Inorganic Heterojunctions for Functional Device Applications

Acknowledgments: This work was supported by the Natural Science Foundation of China (21825103), the China Postdoctoral Science Foundation (2019M662607 and 2019TQ0103), the Hubei Provincial Natural Science Foundation of China (2019CFA002), and the Fundamental Research Funds for the Central University (2019kfyXMBZ018).

MOS-AK Workshop at THM Giessen - 2nd Announcement

--------- Forwarded message ---------
From: Alexander Kloes <alexander.kloes@ei.thm.de>Dear colleagues and friends,

the Joint Spring MOS-AK Workshop 

and Symposium on Schottky Barrier MOS (SB-MOS) devices 

with IEEE EDS Mini-Colloquium 

on „Non-conventional Devices and Technologies" 

is approaching. We decided for a virtual event due to the still present COVID-19 pandemic and regulations worldwide. The event will take place in Zoom as live presentations. The number of attendees is limited to 300 participants. Therefore, we recommend to register for the MOS-AK, Symposium of SB-MOS and IEEE EDS MQ by use of IEEE vTools with following link: https://meetings.vtools.ieee.org/m/205571

Registered attendees will receive the Zoom link for the event a few days before via email from vTools. Presenters will receive an additional link for advance testing of their presentation setup. The registration is for free.

Our joint R&D event will start on September 29^th at 9:15am with a MOS-AK workshop. The MOS-AK workshop will continue on September 30^th morning to noon. In the afternoon, the IEEE EDS Mini-Colloquium „Non-Conventional Devices and Technologies" will take place and will continue during the morning of  October 1^st . In the afternoon, the Symposium on SB-MOS will be held. 

I would like to inform you, that the preliminary program is now available online. 
You can find it at https://ssbmos.blogspot.com/p/programm-2020.html

Best papers will be selected for a special Solid-State-Electronics (SSE) compact modeling issue of MOS-AK activities. 

Attendees are welcome to participate in our joint R&D event. Further information is present at

Symposium of SBMOS
https://ssbmos.blogspot.com
and
MOS-AK
http://www.mos-ak.org/giessen_2020

Important new dates: 
1st Event Announcement: Aug. 2020 
2nd Event Announcement: Sept. 2020 
Final Workshop Program: Sept. 2020
Registration deadline: Sept. 21, 2020
"Spring" MOS-AK Workshop: Sept. 29/30, 2020 
IEEE MQ: Sept. 30/Oct. 1, 2020
Symposium SB-MOS devices: Oct. 1, 2020

Best regards

Alexander Kloes

_____________________________________________________________

Prof. Dr.-Ing. Alexander Kloes

 

Technische Hochschule Mittelhessen - University of Applied Sciences

Department Electrical Engineering and Information Technology

Spokesperson of Competence Center Nanotechnology and Photonics

Director of Doctoral Theses at Universitat Rovira i Virgili, Tarragona

Wiesenstrasse 14

D-35390 Giessen

Germany

E-mail: alexander.kloes@ei.thm.de

Web: go.thm.de/dmrg-en and www.thm.de

[JICS] SBMicro2020 Special Section Issue

Journal of Integrated Circuits and Systems

SBMicro2020 Special Section Issue

Vol 15 No 2 (2020)

The Journal of Integrated Circuits and Systems is an effort of both Brazilian Microelectronics Society - SBMicro and Brazilian Computer Society - SBC to create a new scientific journal covering intended to present state-of-art papers on Integrated Circuits and Systems, covering the fields of Process and Materials, Device and Characterization, Design, Test and CAD, among other relevant topics. The JICS is indexed in Scopus and Scimagojr.

SBMicro2020 Special Section Guest Editors:
Durga Misra, New Jersey Institute of Technology – NJIT, United States
Michelly de Souza, Centro Universitário FEI, Brazil

Online ISSN: 1872-0234 (from 2017 on)
Printed ISSN: 1807-1953 (prior to 2017)
Published: 2020-08-23

[paper] Bulk CMOS Technology at Sub-Kelvin Temperature

Characterization and Modeling of 0.18µm Bulk CMOS Technology 

at Sub-Kelvin Temperature 

Teng-Teng Lu^1,2, Zhen Li^1,2, Chao Luo^1,2, Jun Xu², Weicheng Kong³, 

and Guoping Guo¹ (Member, IEEE) 

IEEE J-EDS, vol. 8, pp. 897-904, 2020

DOI: 10.1109/JEDS.2020.3015265.

¹Key Laboratory of Quantum Information, University of Science and Technology of China, Hefei 230026, China 

²Department of Physics, University of Science and Technology of China, Hefei 230026, China 

³Department of Quantum Hardware, Origin Quantum Computing Company Limited, Hefei 230026, China

Abstract: Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

FIG: IDS-VGS curves of large thin TOX NMOS (a,b,e,f) and PMOS (c,d,g,h) devices at sub-kelvin temperature measured (symbols) and simulated (solid lines). 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2016YFA0301700, in part by the National Natural Science Foundation of China under Grant 11625419, in part by the Anhui initiative in Quantum information Technologies under Grant AHY080000, and in part by the USTC Center for Micro and Nanoscale Research and Fabrication.

[paper] Monolithic Pixel Detector in SOI Technology

High spatial resolution monolithic pixel detector in SOI technology 

R. Bugiel^a1, S. Bugiel^a2, D. Dannheim_b, A. Fiergolski^b, D. Hynds^b,3, M. Idzik^a, P. Kapusta^c, M. Munker^b, A. Nurnberg^b4, S. Spannagel^b,5, K. Swientek^a, W. Kucewicz^a

^aAGH-UST, Poland, ^bCERN, Switzerland, ^cIFJ PAN, Poland

CLICdp-Pub-2020-004

06 August 2020

¹Present: CNRS/IPHC, France.

²Present: CNRS/IPHC, France.

³Present: NIKHEF, Amsterdam, Netherlands.

⁴Present: KIT, Karlsruhe, Germany.

⁵Present: DESY, Hamburg, Germany.

Abstract: This paper presents test-beam results of monolithic pixel detector prototypes fabricated in 200nm Silicon-On-Insulator (SOI) CMOS technology studied in the context of high spatial resolution performance. The tested detectors were fabricated on a 500µm thick highresistivity Floating Zone type n (FZ-n) wafer and on a 300 µm Double SOI Czochralski type p (DSOI Cz-p) wafer. The pixel size is 30µm×30µm and two different front-end electronics architectures were tested, a source follower and a charge-sensitive preamplifier. The test-beam data analyses were focused mainly on determination of the spatial resolution and the hit detection efficiency. In this work different cluster formation and position reconstruction methods are studied. In particular, a generalization of the standard η-correction adapted for arbitrary cluster sizes, is introduced. The obtained results give in the best case a spatial resolution of about 1.5µm for the FZ-n wafer and about 3.0µm for the DSOI Cz-p wafer, both detectors showing detection efficiency above 99.5%.

Fig.: Simplified schematics of Silicon-On-Insulator structures. The Buried N(P)-Well (BN(P)W) is a layer dedicated to shielding the electronics from the sensors electric field.

Aknowlegement: This work was financed by the European Union Horizon 2020 Marie Sklodowska-Curie Research and Innovation Staff Exchange program under Grant Agreement no. 645479 (E-JADE) and also by the Polish Ministry of Science and Higher Education from funds for science in the years 2017 – 2018 allocated to an international co-financed project. The authors would like to thank also the operators of the CERN SPS beam line and North Area test facilities.