2017 IEEE Andrew S. Grove Award

Prof. Sorin Cristoloveanu,  CNRS at IMEP-LAHC

2017 IEEE Andrew S. Grove Award Recipient

“For contributions to silicon-on-insulator technology and thin body devices”

A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits. An IEEE Fellow, Cristoloveanu is the director of research at CNRS at IMEP-LAHC, Grenoble, France [read more...]

[paper] Artificial neural network design for compact modeling of generic transistors

Artificial neural network design for compact modeling of generic transistors

(J Comput Electron; pp. 1-8;  2017)

Lining Zhang and Mansun Chan

Department of ECE, Hong Kong University of Science and
Technology, Kowloon, Hong Kong

Abstract: A methodology to develop artificial neural network (ANN) models to quickly incorporate the characteristics of emerging devices for circuit simulation is described in this work. To improve the model accuracy, a current and voltage data preprocessing scheme is proposed to derive a minimum dataset to train the ANN model with sufficient accuracy. To select a proper network size, four guidelines are developed from the principles of two-layer network. With that, a reference ANN size is proposed as a generic three-terminal transistor model. The ANN model formulated using the proposed approach has been verified by physical device data. Both the device and circuit-level tests show that the ANN model can reproduce and predict various device and circuits with high accuracy [read more...]

(Published online April 9, 2017 http://dx.doi.org/10.1007/s10825-017-0984-9)

Starting Framework of the IRDS Roadmap

IEEE has announced the next milestone phase in the development of the International Roadmap for Devices and Systems (IRDS), an IEEE Standards Association (IEEE-SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative with the launch of a series of nine white papers that reinforce the initiative’s core mission and vision for the future of the computing industry. The white papers also identify industry challenges and solutions that guide and support future roadmaps created by IRDS [read more...]

The series of white papers delivers the starting framework of the IRDS roadmap - and through the sponsorship of IEEE RC—will inform the various roadmap teams in the broader task of mapping the devices’ and systems’ ecosystem:

• Applications Benchmarking
• More Moore
• Beyond CMOS (Emerging Research Devices)
• Outside System Connectivity
• Factory Integration
• Metrology
• Environment, Safety, and Health
• Yield Enhancement
• System and Architecture

The IRDS leadership team hosted a winter workshop and kick-off meeting at the Georgia Institute of Technology on 1-2 December 2016. Key discoveries from the workshop included the international focus teams’ plans and focus topics for the 2017 roadmap, top-level needs and challenges, and linkages among the teams. Additionally, the IRDS leadership invited presentations from the European and Japanese roadmap initiatives. This resulted in the 2017 IRDS global membership expanding to include team members from the “NanoElectronics Roadmap for Europe: Identification and Dissemination” (NEREID) sponsored by the European Semiconductor Industry Association (ESIA), and the “Systems and Design Roadmap of Japan” (SDRJ) sponsored by the Japan Society of Applied Physics (JSAP).

The IRDS team and its supporters will convene 1-3 April 2017 in Monterey, California, for the Spring IRDS Workshop, which is part of the 2017 IEEE International Reliability Physics Symposium (IRPS). The team will meet again for the Fall IRDS Conference in partnership with the 2017 IEEE International Conference on Rebooting Computing (ICRC) scheduled for 6-7 November 2017 in Washington, D.C. More information on both events can be found here.

IEEE RC is a program of IEEE Future Directions, designed to develop and share educational tools, events, and content for emerging technologies [read more...]

NIST Digital Library of Mathematical Functions

Project News

• 2016-12-21 DLMF Update; Version 1.0.14
• 2016-09-16 DLMF Update; Version 1.0.13
• 2016-09-09 DLMF Update; Version 1.0.12
• 2016-06-08 Future expansion
• More news

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Foreword Preface Mathematical Introduction 1 Algebraic and Analytic Methods 2 Asymptotic Approximations 3 Numerical Methods 4 Elementary Functions 5 Gamma Function 6 Exponential, Logarithmic, Sine, and Cosine Integrals 7 Error Functions, Dawson’s and Fresnel Integrals 8 Incomplete Gamma and Related Functions 9 Airy and Related Functions 10 Bessel Functions 11 Struve and Related Functions 12 Parabolic Cylinder Functions 13 Confluent Hypergeometric Functions 14 Legendre and Related Functions 15 Hypergeometric Function 16 Generalized Hypergeometric Functions & Meijer G-Function 17 q-Hypergeometric and Related Functions 18 Orthogonal Polynomials 19 Elliptic Integrals

20 Theta Functions 21 Multidimensional Theta Functions 22 Jacobian Elliptic Functions 23 Weierstrass Elliptic and Modular Functions 24 Bernoulli and Euler Polynomials 25 Zeta and Related Functions 26 Combinatorial Analysis 27 Functions of Number Theory 28 Mathieu Functions and Hill’s Equation 29 Lamé Functions 30 Spheroidal Wave Functions 31 Heun Functions 32 Painlevé Transcendents 33 Coulomb Functions 34 3j, 6j, 9j Symbols 35 Functions of Matrix Argument 36 Integrals with Coalescing Saddles Bibliography Index Notations List of Figures List of Tables Software Errata

[paper] Pulsed I-V on TFETs: Modeling and Measurements

Pulsed I-V on TFETs: Modeling and Measurements
Quentin Smets, Anne Verhulst, Ji-Hong Kim, Jason P. Campbell, David Nminibapiel, Dmitry Veksler, Pragya Shrestha, Rahul Pandey, Eddy Simoen, David Gundlach, Curt Richter, Kin P. Cheung, Suman Datta, Anda Mocuta, Nadine Collaert, Aaron V.-Y. Thean, and Marc M. Heyns
in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1489-1497, April 2017
doi: 10.1109/TED.2017.2670660

Abstract: Most experimental reports of tunneling field-effect transistors show defect-related performance degradation. Charging of oxide traps causes Fermi-level pinning, and Shockley–Read–Hall (SRH)/trap-assisted tunneling (TAT) cause unwanted leakage current. In this paper, we study these degradation mechanisms using the pulsed I-V technique. Our simulations show pulsed I-V can fully suppress oxide trap charging, unlike SRH and TAT. We discuss several circuit-related pitfalls, and we demonstrate improved transfer characteristics by suppressing oxide trap charging using cryogenic pulsed I-V [read more...]