[paper] Statistical model of the NBTI-induced ΔVth, ΔSS, and Δgm degradations in advanced pFinFETs

Statistical model of the NBTI induced threshold voltage, subthreshold swing, and transconductance degradations in advanced pFinFETs
J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta
2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 15.3.1-15.3.4.
DOI: 10.1109/IEDM.2016.7838422

Abstract

We study the stochastic NBTI degradation of pFinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak g m improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of g m aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits. Selected nanoscale device characteristics resulting from 3 percolation paths, generated with the EKV model [read more...]

Publication stats: 1260 Reads

1260 Reads: Open-source circuit simulation tools for RF compact semiconductor device modelling

Article · Sep 2014 · International Journal of Numerical Modelling Electronic Networks Devices and Fields

[paper] Impact of technology scaling on analog and RF performance of SOI–TFET

Impact of technology scaling on analog and RF performance of SOI–TFET

P Kumari, S Dash and G P Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4 

Published 9 October 2015

Abstract

This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD Sentaurus device simulation results [read more...]

Citations
[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al  2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al  2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al  2015 447
   

[paper] Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

S. Golara, S. Moloudi and A. A. Abidi, " 

in IEEE Transactions on Circuits and Systems I: Regular Papers, 

vol. 64, no. 2, pp. 245-260, Feb. 2017; doi: 10.1109/TCSI.2016.2604000

Abstract: Using an appropriate formulation of field-effect transistor (FET) current as a nonlinear function of terminal voltages, and a simplified model of gain compression in common source amplifiers, we are able to identify four principal sources of amplitude-to-phase (AM-PM) distortion. A new analysis shows the varactor effect of gate-source capacitance on AM-PM distortion, and the changing Miller-multiplied gate-drain capacitance as the field-effect transistor (FET) is driven into compression. The phase shift in the load impedance at the frequency of operation and incomplete suppression of 2nd harmonic by a resonant load of limited Q are explained and analyzed. We are able to identify the dominant mechanism of AM-PM distortion in various practical circuits, which then suggests methods of remediation. The analysis was put to test by predicting the measured AM-PM distortion of power amplifiers reported in the literature. Good agreement is found in all cases, with insights gained into the dominant cause of distortion in each case. In this paper, AM-PM distortion is first defined in Section II. In Section III, the EKV model of the MOSFET is briefly presented and dominant mechanisms are explained. In Section IV the analysis is compared against measured data to validate the theory and Section V summarizes the conclusions [read more...]

IEEE Workshop on Compact Modeling

IEEE Workshop on Compact Modeling

March 3, 2017

Technical Sponsorship by: IEEE Electron Devices Society UP Chapter

Organized by: Department of Electrical Engineering, IIT Kanpur

Coordinator: Prof. Yogesh Singh Chauhan

Venue: Outreach Auditorium, IIT Kanpur

IEEE Workshop on Compact Modeling Agenda:

Time	Topic	Speaker
8:00 - 8:15	Workshop inauguration by Director IIT Kanpur and IEEE-UP Chairman
8:15 - 9:00	Industry Standard Compact Modelling	Dr. Yogesh Singh Chauhan IIT Kanpur
9:00 - 9:30	Modelling of mismatch and process variations	Dr. Abhisek Dixit IIT-Delhi
9:30 - 10:00	TBA	Dr. Nihar Ranjan Mohapatra IIT-Gandhinagar
10:00 - 10:30	Modelling of normally-off GaN based MOSHEMT	Dr. Trupti Ranjan Lenka NIT Silchar
10:30 - 10:45	ASM-HEMT: Industry standard compact model for GaN HEMTs	Dr. Sudip Ghosh IIT-Kanpur
10:45 - 11:00	Modelling of quasi ballistic transport in nano-wire transistors	Mr. Avirup Dasgupta IIT Kanpur
11:00 - 11:15	TBA	Mr. Priyank Rastogi IIT Kanpur
11:15 - 11:30	Compact modelling of TMD based thin body transistors	Mr. Chandan Yadav IIT Kanpur
11:30 - 11:45	Tea Break
11:45 - 12:15	Qualification techniques for sim models for EEsof products	Mr. Mohit Khanna Keysight Technologies
12:15 - 12:45	High frequency device characterization and modeling for THz applications	Prof. Thomas Zimmer IMS-BORDEAUX
12:45 - 2:00	Lunch
2:00 - 2:30	Device design consideration: IoT perspective	Dr. Santosh Kumar Vishvakarma IIT-Indore
2:30 - 3:00	TBA	Dr. Aditya Sankar Medury IISER-Bhopal
3:00 - 3:30	Simulations, analysis and applications of doping- and junction- free transistors	Dr. Jawar Singh IIIT-Jabalpur
3:30 - 4:00	Design of radiation hardened 24-bit ADC for generic applications	Mr. H.S.Jattana SCL
4:00 - 4:15	Tea Break
4:15 - 4:45	Role of Feynman diagrams in energy band structure of materials - A post density functional theory approach	Dr. Sitangshu Bhattacharya IIIT-Allahabad
4:45 - 5:15	TBA	Dr. Swaroop Ganguly IIT-Bombay
5:15 - 5:45	TBA	Dr. Saurabh Lodha IIT-Bombay
5:45 - 6:15	TBA	Dr. Udayan Ganguly IIT-Bombay
6:15 - 6:45	TBA	Dr. Manoj Saxena Delhi University
6:45 - 7:00	Closing Keynote