Parasitic Capacitance Analytical #Modeling for Sub-7-nm Multigate Devices https://t.co/z8Q8IcuINM

Parasitic Capacitance Analytical #Modeling for Sub-7-nm Multigate Devices https://t.co/z8Q8IcuINM

— Wladek Grabinski (@wladek60) January 22, 2016

from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:47PM
via IFTTT

Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices #modeling https://t.co/9Q50HGFkni

Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices #modeling https://t.co/9Q50HGFkni

— Wladek Grabinski (@wladek60) January 22, 2016

from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:44PM
via IFTTT

FOSDEM 2016 EDA Devroom

FOSDEM 2016: EDA Devroom

Room: AW1.121 

Saturday, 30 January 2016

Software developers have a much easier time sharing their developments than hardware designers. When you put a piece of code on the Web, you don't ask yourself if others will have the freedom and resources to access a text editor to look at it and modify it, or a compiler or interpreter to have the code do something useful. The landscape for hardware designs is more complicated. The dominant design and simulation tools are proprietary, and there is not even a de-facto proprietary standard format to share designs. The Electronic Design Automation (EDA) Devroom looks at recent progress in Free CAD/EDA Tools for hardware design and simulation, and serves as a meeting place for discussion about future collaborations and FOSS developments. Come and see how some of these tools are actually catching up, and sometimes even more, in terms of features and quality.

[EDA Devroom Detailed Agenda]

NEEDS Berkeley Workshop 2016

Modelling using Verilog-A in MAPP: A Hands-On Workshop

8 AM - 6 PM

Thursday, Feb 4, 2016

University of California, Berkeley

Hughes Room, 400 Cory Hall

Berkeley, CA 94720

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Berkeley's Model and Algorithm Prototyping Platform (MAPP) is a MATLAB-based platform that provides a complete environment for developing, testing, experimentally validating, and inserting compact models in open source simulation platforms. It is also useful for prototyping new simulation algorithms.

This hands-on workshop will focus on the newly developed Verilog-A to ModSpec device model translator for MAPP, dubbed VAPP (Verilog-A Parser and Processor). The goal of the workshop is to illustrate how VAPP/MAPP facilitates the development of simulation ready compact models. An overview of MAPP's multi-physics modelling and simulation capabilities will also be provided. A hands-on refresher on MAPP will be provided for those who have no prior experience with it.

Please bring your laptop (running linux, OSX or Windows). It would be very helpful if you already have MATLAB installed and running on your laptop; otherwise you may need to access the hands-on components through the web.

For more information about MAPP, see: https://nanohub.org/groups/needs/mapp

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Travel support will be available for NEEDS students. Please try to share a room, and ask your advisor to e-mail Mark Lundstrom at lundstro@purdue.edu for travel support.

For other questions, please contact Vicki Johnson at vicki@purdue.edu

[video] How to Model RF Passive Components: Capacitors and Resistors

This video explains and demonstrates a method to develop accurate SPICE models from verified S-parameter measurements. By using an easy to follow, step by step procedure, this video walks you through the entire modeling flow for an on-wafer capacitor, using the Keysight Measurement and Modeling Software IC-CAP.

The IC-CAP project can be downloaded, together with a detailed How-to-Use description, and an in-depth tutorial about passive components modeling, applying the demonstrated method.

[VIDEO]