Where to study nanotech?

Marie Curie Fellows - Centro de Química da Madeira, Funchal, Madeira Island, Portugal.

Job Reference: CQM-WIIP-2010

Where to study nanotech in India?

Nanotechnology in USA

Visit also Nanotechnology - TINC

Accelicon announces Context Dependent Modeling Platform

I copy a part of the original post:

Accelicon Technologies, Inc. announces the market’s first commercially available Context Dependent Modeling Platform based on Accelicon’s flagship device modeling solution MBP. The performance of FETs can vary significantly, at advanced process nodes, due to layout dependent proximity effects. Sources of LDEs include Well Proximity Effect (WPE), lithography distortions, un-intentional stress sources such as Shallow Trench Isolation (LOD Effect) and intentional stressors which are used to enhance the performance of the device. These enhancement techniques include dual-stress liners, embedded SiGe and stress memorization techniques. At advanced process nodes engineers must analyze LDEs to minimize undesirable proximity effects and lithography distortions, and effectively utilize stress enhancement techniques. This analysis can only be conducted after layout extraction, SPICE modeling alone is not sufficient. 

Read more at the original post in LinkedIn:

Accelicon announces Context Dependent Modeling Platform

Simulating the Memristor with spice (as of September 2010)

Here you have a list of papers where people model a memristor:


- H.H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," DATE, 2010.

- Á. Rak and G. Cserey, "Macromodeling of the Memristor in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, 2010, pp. 632-636.

- D. Batas and H. Fiedler, "A Memristor Spice Implementation and a New Approach for Magnetic Flux Controlled Memristor Modeling," IEEE Transactions on Nanotechnology, 2010, pp. 1-1.

- "Modeling the HP memristor with SPICE," http://www.neurdon.com/2010/07/23/modeling-the-hp-memristor-with-spice/, 2010.

- Valsa, J., Biolek, D. and Biolek, Z. , "An analogue model of the memristor". International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, n/a. doi: 10.1002/jnm.786

Lot of work, isn't it?

www.SoCconference.com

8th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Date: Nov. 3-4, 2010
Venue: Hilton Irvine/Orange County Airport
Agenda & Schedule

Early Bird Registration Is Now Open!

Three distinguished keynote speakers:

1. Dr. Ivo Bolsens, Senior Vice President and CCEO, Xilinx Inc.

2. Dr. J. Antonio Carballo, WW Manager, IBM Microelectronics Services, Semiconductor Partner, IBM VC Group, IBM.

3. Raouf Y. Halim, CEO, Mindspeed Technologies, Inc.

New record set for ferroelectric data storage

Scanning Nonlinear Dielectric Microscope: inset left: Shows topography and electric dipole-moment; inset right: Example of a ferroelectric information storage; [Read more...]