#NanoElectronics Roadmap for #Europe: From Nanodevices and Innovative Materials to System Integration, Solid-State Electronics, 2019 https://t.co/BQz3vAjItM https://t.co/BQz3vAjItM https://t.co/miwhM4i69s #paper

#NanoElectronics Roadmap for #Europe: From Nanodevices and Innovative Materials to System Integration, Solid-State Electronics, 2019 https://t.co/BQz3vAjItMhttps://t.co/BQz3vAjItM https://t.co/miwhM4i69s #paper

— Wladek Grabinski (@wladek60) March 7, 2019

from Twitter https://twitter.com/wladek60

March 07, 2019 at 10:15PM
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#PAPER • OPEN ACCESS Gallium Nitride FET Model V V Orlov and G I Zebrev 2019 IOP Conf. Ser.: Mater. Sci. Eng. 475 012007 https://t.co/gV4Ijifd5g

#PAPER • OPEN ACCESS
Gallium Nitride FET Model
V V Orlov and G I Zebrev 2019 IOP Conf. Ser.: Mater. Sci. Eng. 475 012007 https://t.co/gV4Ijifd5g

— Wladek Grabinski (@wladek60) March 7, 2019

from Twitter https://twitter.com/wladek60

March 07, 2019 at 09:38PM
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S. Amer, M. S. Hasan, M. M. Adnan and G. S. Rose, "#SPICE #Modeling of Insulator Metal Transition: Model of the Critical Temperature," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 18-25, 2019. doi: 10.1109/JEDS.2018.2875627 https://t.co/it8osJWSPM https://t.co/vvGAsWCeYY

S. Amer, M. S. Hasan, M. M. Adnan and G. S. Rose, "#SPICE #Modeling of Insulator Metal Transition: Model of the Critical Temperature," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 18-25, 2019.
doi: 10.1109/JEDS.2018.2875627 https://t.co/it8osJWSPM pic.twitter.com/vvGAsWCeYY

— Wladek Grabinski (@wladek60) March 6, 2019

from Twitter https://twitter.com/wladek60

March 06, 2019 at 07:30PM
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Special MDPI Issue Field-Effect Transistors for Chemical Sensors https://t.co/0w9pQgMqlo #paper https://t.co/nd5EUX1KeD

Special MDPI Issue Field-Effect Transistors for Chemical Sensors https://t.co/0w9pQgMqlo #paper pic.twitter.com/nd5EUX1KeD

— Wladek Grabinski (@wladek60) March 6, 2019

from Twitter https://twitter.com/wladek60

March 06, 2019 at 08:01PM
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#EMM to offer its ultra low power 180nm #CMOS for #MPW service https://t.co/beBG061h9y #model https://t.co/6MOVGvrX97

#EMM to offer its ultra low power 180nm #CMOS for #MPW service https://t.co/beBG061h9y #model pic.twitter.com/6MOVGvrX97

— Wladek Grabinski (@wladek60) March 4, 2019

from Twitter https://twitter.com/wladek60

March 04, 2019 at 10:26PM
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F. Jazaeri and J. Sallese, "Charge-Based EPFL HEMT #Model," in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1218-1229, March 2019. https://t.co/rFwjVUuRbM

F. Jazaeri and J. Sallese, "Charge-Based EPFL HEMT #Model," in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1218-1229, March 2019. https://t.co/rFwjVUuRbM

— Wladek Grabinski (@wladek60) March 1, 2019

from Twitter https://twitter.com/wladek60

March 01, 2019 at 02:15PM
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IIT Kanpur: open compact modeling position

Indian Institute of Technology, Kanpur

The Office of Research & Development

Date: 15-02-2019

Indian Institute of Technology, Kanpur an Institute of national importance, has been in the forefront of engineering & technology education and research & development. The Institute derives strength from its philosophy, vision and values that has led to achievement of academic excellence and promotion of high order technological research. The Institute's R&D Division is looking for suitable Indian nationals including Persons of Indian Origins (PIOs) and Overseas Citizens of India (OCIs) for appointment on the following positions for short-term R&D Projects on contractual basis for a period of maximum five years.

Please forward this job opening with following requirements to your friends/colleagues.

http://iitk.ac.in/new/RnD_Recruitment/

• Hands-on experience of I-V (DC and Pulsed), CV, RF (CW and Pulsed)
• Expertise in Semiconductor Device Modeling and Simulation softwares
• PDK Development & Layout design
• Knowledge of Verilog-A language, PEL/ Python script.
• Strong background in semiconductor device physics
• Good writing skills
• Good Project Management skills

#FOSDEM 2019 – Space and Meaning https://t.co/mQqeuvwtrN #paper

#FOSDEM 2019 – Space and Meaning https://t.co/mQqeuvwtrN #paper

— Wladek Grabinski (@wladek60) February 17, 2019

from Twitter https://twitter.com/wladek60

February 17, 2019 at 10:45PM
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[mos-ak] 2019 IEEE International Conference on Modeling of Systems Circuits and Devices

2019 IEEE International Conference on Modeling of Systems Circuits and Devices

(MOS-AK/India 2019)

Organized by Joint Chapters of CAS / EDS Societies

IEEE Hyderabad Section

Together with the lead sponsors and the conference organization committee we have pleasure to invite to consecutive, 2nd MOS-AK/India Compact Modeling Conference to be hosted at the IIT Hyderabad

Announced, subsequent 2nd MOS-AK/India Conference organized at the IIT Hyderabad, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <http://www.mos-ak.org/india_2019/>

Dates:

MOS-AK/India Conference - February 25-27, 2019

Feb. 25      - ONE day SPICE/Verilog-A Modeling Tutorials

Feb. 26-27 - TWO days SPICE/Verilog-A Modeling Conference

Venue:

Indian Institute of Technology (IIT)

Hyderabad, Kandi

Telangana State, India

Online registration (any related enquiries can be sent secretary.mosak.india@gmail.com or call 9652158557) 

W.Grabinski on the behalf of International MOS-AK Committee

WG02092019

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IEEE EDS MQ at Hotel Plaza, Begumpet (IN)

Joint Chapter of Electron Devices and Circuits and Systems Societies (ED/CAS)

presents

IEEE Electron Devices Mini Colloquia

Date:  Sunday, 24 February 2019 Time:  3.00 P.M to 6.00 P.M

Venue: Hotel Plaza, Begumpet. Free Registration Link 

For any further details please contact the MQ Coordinators:

• Dr. Mohammed Arifuddin Sohel, Chair, IEEE CAS/EDS joint Chapter
• Dr. A.G. Krishna Kanth, Vice Chair, IEEE CAS/EDS joint Chapter

Registrations: 3:00PM to 3.15 PM

DL Talk 1: 3.15 PM to 4.00PM, Speaker: Prof. Charvaka Duvvury, iT2 Technologies (USA)
Topic: ESD Issues and Challenges for Advanced Semiconductor Technologies

Electro-static Discharge (ESD) has been a constant reliability concern for IC technologies for several decades and it is heading to be a roadblock to newer applications for electronic devices. The seminar will begin with a summary of the understanding about ESD and how this is applied to develop protection at the IC level for Digital, Analog, and RF circuits. This will be followed by a review of the problems posed by advanced technologies beyond the 32 nm node and the corresponding challenge of hitting the available ESD design window while meeting the IO high-speed performance requirements. The talk will conclude with a survey of the upcoming challenges from emerging technologies such as GaN and CNT, as well as IoT applications. 

Speaker Bio: Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI.  He received his PhD in engineering science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta. His experience at Texas Instruments spanned for 35 years in semiconductor device physics with pioneering development work in ESD design. He has also mentored PhD students at several leading US universities on their investigations in ESD research and received Outstanding Industry Mentor Award twice from the SRC. Charvaka has published over 150 papers in technical journals and conferences and holds more than US 75 patents. He co-authored and contributed to 5 books on the subject. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine and machine learning for rapid ESD data analysis. Charvaka is also Fellow of the IEEE.

Hi Tea and Networking: 4.00 PM to 4.15 PM

DL Talk 2: 4.15 PM to 5.00PM Speaker: Dr. Wladek Grabinski, MOS-AK (Switzerland)

Topic: FOSS TCAD/EDA Process/Device Simulations for Compact/SPICE Modeling

Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce.

Speaker Bio: Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. Wladek is the chair of the ESSDERC Track4: "Device and circuit compact modeling" as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ/ Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

DL Talk 3: 5.00PM to 5.45 PM Speaker: Prof. Roberto Murphy, INAOE (Mexico)
Topic: Fundamental Aspects of CMOS RF Modeling and Characterization

As CMOS technology evolves, higher frequencies can be attained while more complex functions and operations become possible in Integrated Circuits. At the design stage, there are several fundamental aspects which have to be taken into account in order to have successful fabrication results, the closest to simulation predictions as possible. Furthermore, this evolution leads to more time-consuming characterization routines, which require both personnel and time to be performed. Some of the aspects dealt with in this talk refer to characterization techniques, substrate network effects, and geometry effects.

Speaker Profile:  Roberto S. Murphy-Arteaga (M´92, SM´02) received his B.Sc. degree in Physics from St. John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from the National Institute for Research on Astrophysics, Optics and Electronics (INAOE), in Tonantzintla, Puebla, México.  He has been a researcher at INAOE since 1988. Since then, he has presented over 110 talks at scientific conferences, directed nine Ph.D. theses, 16 M.Sc. and 2 B.Sc. theses, published more than 140 articles in scientific journals, conference proceedings and newspapers, and is the author of a text book on Electromagnetic Theory.  He is currently a senior researcher with the Microelectronics Laboratory.  Dr. Murphy’s research interests are the physics, modeling and characterization of the MOS Transistor and passive components for high frequency applications, especially for CMOS wireless circuits, and antenna design.  For the last 30 years, he has been active in the organization of conferences, mostly in Latin America, such as the IEEE International Caribbean Conference on Devices, Circuits and Systems; the Latin American Symposium on Circuits and Systems; VLSI-SoC, and others related to microelectronics and IC design. He is a Senior Member of IEEE, a Distinguished Lecturer of the Electron Devices Society, the President of ISTEC, a member of the Mexican Academy of Sciences, and a member of the Mexican National System of Researchers (SNI).

If #Software Is Funded from a #Public Source, Its Code Should Be #OpenSource https://t.co/ZFzJE3SfGK https://t.co/Hq4oF9yqgp

If #Software Is Funded from a #Public Source, Its Code Should Be #OpenSource https://t.co/ZFzJE3SfGK pic.twitter.com/Hq4oF9yqgp

— Wladek Grabinski (@wladek60) February 5, 2019

from Twitter https://twitter.com/wladek60

February 05, 2019 at 08:56PM
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#MIXDES: #Paper submission deadline reminder (4 weeks left) https://t.co/Iw6yG0q157 This year the 26th MIXDES will take place between June 27-29, 2019 in Rzeszów (PL) https://t.co/ewrq66xLoK

#MIXDES: #Paper submission deadline reminder (4 weeks left)https://t.co/Iw6yG0q157
This year the 26th MIXDES will take place between June 27-29, 2019 in Rzeszów (PL) pic.twitter.com/ewrq66xLoK

— Wladek Grabinski (@wladek60) February 4, 2019

from Twitter https://twitter.com/wladek60

February 04, 2019 at 02:55PM
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GnuCap and ngspice at 2019 FOSDEM DevRoom CAD and Open Hardware

Today at #FOSDEM: Felix Salfelder presenting "#Gnucap -- The GNU circuit analysis package Architecture, Algorithms and Applications" addressing Compact Model license considerations
"https://buff.ly/2CeG4DV"


Holger Vogt presenting "#ngspice, current status and future developments" pointing to an obstacle in FOSS CAD/EDA adoption: The newer and more complex Libs/PDKs often come along with encrypted model files.
"https://buff.ly/2DR0Fz6"

RT @devsim: New DEVSIM TCAD Simulator Release https://t.co/q4fiJ9IMWK #tcad #devsim #opensource https://t.co/T4CLcTTQTO

RT @devsim: New DEVSIM TCAD Simulator Releasehttps://t.co/q4fiJ9IMWK #tcad #devsim #opensource https://t.co/T4CLcTTQTO

— Wladek Grabinski (@wladek60) February 1, 2019

from Twitter https://twitter.com/wladek60

February 01, 2019 at 09:00AM
via IFTTT

#IJNM #paper Ye Yuan Zheng Zhong Yong‐xin Guo Shanxiang Mu A novel large‐signal FET model considering trapping‐induced dispersions https://t.co/UYndQ8cKK1” https://t.co/vu0WQtnRgr https://t.co/BiU9XDDiZc

#IJNM #paper Ye Yuan Zheng Zhong Yong‐xin Guo Shanxiang Mu A novel large‐signal FET model considering trapping‐induced dispersions https://t.co/UYndQ8cKK1” https://t.co/vu0WQtnRgr pic.twitter.com/BiU9XDDiZc

— Wladek Grabinski (@wladek60) January 31, 2019

from Twitter https://twitter.com/wladek60

January 31, 2019 at 04:30PM
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Multiphysics Simulation of Biosensors

M. Madec, L. Hébrard, J. Kammerer, A. Bonament, E. Rosati and C. Lallement

Multiphysics Simulation of Biosensors Involving 3D Biological Reaction-Diffusion Phenomena in a Standard Circuit EDA Environmen

IEEE Transactions on Circuits and Systems I: Regular Papers.

doi: 10.1109/TCSI.2018.2885223

Abstract: The topic of this paper is the development of biological models for 3D reaction-diffusion phenomena that can be used in any circuit electronic design automation environment for the simulation of biosensors. Biological systems that involve such 3D phenomena are described by partial differential equations. Our approach consists in discretizing these equations according to the finite-difference method and converting the resulting ordinary differential equations into an assembly of elementary electronic equivalent circuits that are directly simulated with SPICE. The main interest of this approach is the ability to couple such models with third-party SPICE models of electronic circuits, sensors, and transducers, i.e., models from any physical domain ruled by Kirchhoff laws, allowing modeling and simulation of any multi-physics systems in a conventional circuit design environment, here CADENCE. The tool is validated on simple problems for which analytical solutions are known. Then, the interest of the approach is illustrated on the study of a biosensor.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8602461&isnumber=4358591

E.A. Vittoz “CRYSTAL (and MEMS) OSCILLATORS" (course) November 2018 DOI: 10.13140/RG.2.2.25856.07689 https://t.co/NBz9JnZNSL #paper https://t.co/3A1AvRYHd9

E.A. Vittoz “CRYSTAL (and MEMS) OSCILLATORS" (course)
November 2018
DOI: 10.13140/RG.2.2.25856.07689https://t.co/NBz9JnZNSL#paper pic.twitter.com/3A1AvRYHd9

— Wladek Grabinski (@wladek60) January 23, 2019

from Twitter https://twitter.com/wladek60

January 23, 2019 at 10:16AM
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#C4P for a Special Issue of IEEE #TED on Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices https://t.co/0Tcarn2xGC #paper

#C4P for a Special Issue of IEEE #TED on Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices https://t.co/0Tcarn2xGC #paper

— Wladek Grabinski (@wladek60) January 21, 2019

from Twitter https://twitter.com/wladek60

January 21, 2019 at 05:58PM
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A #SPICE Compatible Compact #Model for #Hot-Carrier Degradation in MOSFETs Under Different Experimental Conditions - IEEE Journals & Magazine https://t.co/W7w1zqzXnn

A #SPICE Compatible Compact #Model for #Hot-Carrier Degradation in MOSFETs Under Different Experimental Conditions - IEEE Journals & Magazine https://t.co/W7w1zqzXnn

— Wladek Grabinski (@wladek60) January 19, 2019

from Twitter https://twitter.com/wladek60

January 19, 2019 at 06:15PM
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#roadmap for wider #access to #scientific #results https://t.co/oeNFCdGouJ #opensource https://t.co/DmlOpnUi25

#roadmap for wider #access to #scientific #results https://t.co/oeNFCdGouJ #opensource pic.twitter.com/DmlOpnUi25

— Wladek Grabinski (@wladek60) January 17, 2019

from Twitter https://twitter.com/wladek60

January 17, 2019 at 12:24PM
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#Baidu Announces #OpenSource Edge Computing Platform #OpenEdge https://t.co/PvmANhazM4 https://t.co/7xlZzlMANX

#Baidu Announces #OpenSource Edge Computing Platform #OpenEdge https://t.co/PvmANhazM4 pic.twitter.com/7xlZzlMANX

— Wladek Grabinski (@wladek60) January 16, 2019

from Twitter https://twitter.com/wladek60

January 16, 2019 at 01:58PM
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Environment for #Modeling and #Simulation of #Biosystems, Biosensors, and Lab-on-Chips #LoC - IEEE Journals & Magazine https://t.co/GJpZySIRda

Environment for #Modeling and #Simulation of #Biosystems, Biosensors, and Lab-on-Chips #LoC - IEEE Journals & Magazine https://t.co/GJpZySIRda

— Wladek Grabinski (@wladek60) January 14, 2019

from Twitter https://twitter.com/wladek60

January 14, 2019 at 04:58PM
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#Cryogenic Characterization of 22-nm #FDSOI CMOS Technology for #Quantum #Computing ICs - IEEE Journals & Magazine https://t.co/gg4mCXztz3 #paper

#Cryogenic Characterization of 22-nm #FDSOI CMOS Technology for #Quantum #Computing ICs - IEEE Journals & Magazine https://t.co/gg4mCXztz3 #paper

— Wladek Grabinski (@wladek60) January 14, 2019

from Twitter https://twitter.com/wladek60

January 14, 2019 at 04:56PM
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What #Opening the #MIPS #Architecture Could Mean https://t.co/z43S9tOMNJ #opensource

What #Opening the #MIPS #Architecture Could Mean https://t.co/z43S9tOMNJ #opensource

— Wladek Grabinski (@wladek60) January 13, 2019

from Twitter https://twitter.com/wladek60

January 13, 2019 at 06:58PM
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Postdoctoral positions in device modeling in Spain

As Professor in the in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain., I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, nanowire FETs ,GaN HEMTs, Tunnel FETs, organic and metal oxide TFTs and hyLEDs.

The candidate should be a person who holds a PhD as awarded after January 1 2014.

Contracts will have a duration of two years are expected to start after June 2019.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. 

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

 

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: January 24 2019

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat

 
Benjamin Iñiguez

 

 

 

How #OpenSource Makes Us Better #Human Beings and Brings Us #Together https://t.co/1fUaAVzIqw https://t.co/VHtYEpgD32

How #OpenSource Makes Us Better #Human Beings and Brings Us #Together https://t.co/1fUaAVzIqw pic.twitter.com/VHtYEpgD32

— Wladek Grabinski (@wladek60) January 11, 2019

from Twitter https://twitter.com/wladek60

January 11, 2019 at 09:44AM
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An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model

Ravi Goel, Chetan Gupta, Yogesh S. Chauhan

EE Department, Indian Institute of Technology Kanpur, Kanpur, India

Published in: 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)

Abstract: Recent enhancement in BSIM-BULK (formerly BSIM6) model is presented in this work. The industry standard models like BSIM4, PSP, BSIM-BULK etc. lack the parameters for tuning of transconductance to channel current ratio (gm/Id). gm/Id is also a critical figure of merit for analog applications. Here, we propose an empirical model to enhance the flexibility of gm/Id tuning behavior. The proposed model provides good fitting for different channel lengths and drain bias.

Paper Sections:
I. Introduction
II. An Empirical Model for gm/Id Tuning
III. Model Implementation
IV. Model Validation with TCAD
V. Conclusion

Source:
DOI: 10.1109/UPCON.2018.8597065

#NEXTS Europe secures Europractice services to European academia and industry until end #2021 https://t.co/HsOfzwOY5z #model https://t.co/hXVWSabx05

#NEXTS Europe secures Europractice services to European academia and industry until end #2021 https://t.co/HsOfzwOY5z #model pic.twitter.com/hXVWSabx05

— Wladek Grabinski (@wladek60) January 9, 2019

from Twitter https://twitter.com/wladek60

January 09, 2019 at 02:57PM
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Compact Transcapacitance Model for Short Channel DG FinFETs

Armenian Journal of Physics, vol. 11, issue 4, pp. 269-272

(Proceedings of the Int. Conference on Microwave and THz Technologies and Wireless Comm.)

Ashkhen Yesayan

Institute of Radiophysics and Electronics

Alikhanian Brothers str. 1, 0203 Ashtarak, Armenia

Received 15 November 2018

Abstract: A compact capacitance model is developed accounting for small-geometry effects in FinFETs. While decreasing the channel length, the transcapacitance model becomes very sensitive to all short channel effects, both in moderate and strong inversion regimes. In addition, for short channel devices, we need to take into account the inter-electrode capacitive coupling in the subthreshold regime, which is not significant for long channel devices. The quantum mechanical effects, which are very significant for thin Fins, are included in the model. The effect of mobility degradation on C-V characteristics is also demonstrated. The model was validated with numerical 3D Atlas simulations and a good accuracy of the model has been demonstrated in all operating regimes.

References:

[1] Tech. rep., International technology roadmap for semiconductor (ITRS). 2009.

[2] J.-M. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A. Roy, C. Enz, A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism, Solid-State Electron, vol. 49 no. 3, pp. 485–489. 2005.

[3] A Yesayan, F Prégaldiny, N Chevillon, C Lallement, JM Sallese, Physics-based compact model for ultra-scaled FinFETs, Solid-State Electronics, vol. 62, no1, pp. 165-173, 2011.

[4] Liang X, Taur Y., A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Dev 2004;51(9):1385–91.

[5] Ward D, Dutton R. ,A charge-oriented model for MOS transistor capacitances. IEEE J Solid-State Circ, 1978;13(5):703–8.

[6] Tang M. Etude et modélisation compacte du transistor FinFET. Ph.D. Thesis, University of Strasbourg; December 2009.

[7] Borli H, Vinkenes K, Fjeldly T., Physics-based capacitance modeling of short-channel double-gate MOSFETs. Phys Status Solidi (c) 2008;5(12):3643–6.

[8] Arora N., MOSFET models for VLSI circuit simulation. New York: Theory and Practice, Springer-Verlag; 1993, ISBN:3-211-82395-6

Source:

http://ajp.asj-oa.am/1004/1/EL_4.pdf

#Julia Co-Creators To Receive 2019 James H. Wilkinson #Prize for #Numerical #Software https://t.co/5oLiWnuDZL #opensource

#Julia Co-Creators To Receive 2019 James H. Wilkinson #Prize for #Numerical #Software https://t.co/5oLiWnuDZL #opensource

— Wladek Grabinski (@wladek60) January 9, 2019

from Twitter https://twitter.com/wladek60

January 09, 2019 at 08:12AM
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IEEE TED SI on Compact Modeling for Circuit Design

Special Issue on Compact Modeling for Circuit Design

Benjamin Iñiguez, Wladek Grabinski, Slobodan Mijalković, Kejun Xia, Andries J. Scholten, Yogesh Singh Chauhan, Ananda S. Roy, Sadayuki Yoshitomi, Kaikai Xu

in IEEE Transactions on Electron Devices, vol. 66, no. 1, Jan. 2019.

doi: 10.1109/TED.2018.2884284

Abstract: This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

A total of 60 regular papers were submitted to this Special Issue, of which 21 were accepted. Besides, the Special Issue includes four invited papers. All papers, including the invited ones, were subjected to thorough peer review. A high number of reviewers have participated in this process. This has resulted in a Special Issue containing very high-quality papers.

The published papers target compact modeling aspects for a wide number of devices: several MOSFET structures, tunnel FETs, HEMTs, nanowire FETs, TMD FETs, TFTs, OLEDs, solar cells, photodiodes, and so on.Besides, different operation regimes and analyses are addressed: dc, RF, HV, ballistic regime, variability, reliability, aging, and so on.

The four invited papers also target different topics. The paper by C. C. McAndrew is focused on the successes and challenges of MOS compact models. S. Dongaonkar et al. address the opportunities and challenges of circuit design methodologies ranging from process corners to statistical circuit design. P. Zampardi et al. discuss the industrial view of III–V device compact modeling for circuit design. Finally, Madec et al. target a quite different and challenging environment for the modeling of biosensors, biosystems, and lab-on-chips.

I would like to thank the work done by the rest of the Editors of this Special Issue and also by all the reviewers who participated in this process. And of course, I want to thank all the authors for their interest in submitting papers to this Special Issue. Thanks to authors, reviewers, and editors, this high-quality Special Issue has been possible.

(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

— Wladek Grabinski (@wladek60) December 30, 2018

from Twitter https://twitter.com/wladek60

December 30, 2018 at 08:03PM
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